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2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2018)
Vancouver, British Columbia, Canada
May 21, 2018 to May 25, 2018
ISSN: 1530-2075
ISBN: 978-1-5386-4368-6
pp: 368-377
ABSTRACT
Persistent Memory (PM) and Hardware Transactional Memory (HTM) are two recent architectural developments whose joint usage promises to drastically accelerate the performance of concurrent, data-intensive applications. Unfortunately, combining these two mechanisms using existing architectural supports is far from being trivial. This paper presents NV-HTM, a system that allows the execution of transactions over PM using unmodified commodity HTM implementations. NV-HTM relies on a hardware-software co-design technique, which is based on three key ideas: i) relying on software to persist transactional modifications after they have been committed via HTM; ii) postponing the externalization of commit events to applications until it is ensured, via software, that any data version produced and observed by committed transactions is first logged in PM; ii) pruning the commit logs via checkpointing schemes that not only bound the log space and recovery time, but also implement wear levelling techniques to enhance PM's endurance. By means of an extensive experimental evaluation, we show that NV-HTM can achieve up to 10× speed-ups and up to 11.6× reduced flush operations with respect to state of the art solutions, which, unlike NV-HTM, require custom modifications to existing HTM systems.
INDEX TERMS
checkpointing, hardware-software codesign, storage management
CITATION

D. Castro, P. Romano and J. Barreto, "Hardware Transactional Memory Meets Memory Persistency," 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Vancouver, British Columbia, Canada, 2018, pp. 368-377.
doi:10.1109/IPDPS.2018.00046
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