2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2016)
Chicago, IL, USA
May 23, 2016 to May 27, 2016
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2016.70
Memory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale systems. For memory systems Error Correcting Codes (ECC) are the mostcommonly used mechanism. However state-of-the art hardware ECCs will not be sufficient in terms of error coverage for future computing systems and stronger hardware ECCs providing more coverage have prohibitive costs in terms of area, power and latency. Software-based solutions are needed to cooperate with hardware. In this work, we propose a Cyclic Redundancy Checks (CRCs) based software mechanism for task-parallel HPC applications. Our mechanism incurs only 1.7% performance overheadwith hardware acceleration while being highly scalable at large scale. Our mathematical analysis demonstrates the effectiveness of our scheme and its error coverage. Results show that our CRC-based mechanism reduces the memory vulnerability by 87% on average with up to 32-bit burst (consecutive) and 5-bit arbitrary error correction capability.
Hardware, Error analysis, Fault tolerance, Fault tolerant systems, Programming, Error correction codes
O. Subasi, O. Unsal, J. Labarta, G. Yalcin and A. Cristal, "CRC-Based Memory Reliability for Task-Parallel HPC Applications," 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Chicago, IL, USA, 2016, pp. 1101-1112.