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Parallel and Distributed Processing Symposium, International (2009)
Rome, Italy
May 23, 2009 to May 29, 2009
ISBN: 978-1-4244-3751-1
pp: 1-8
Thomas Zeiser , Erlangen Regional Computing Center, University of Erlangen-Nuremberg, Germany
Georg Hager , Erlangen Regional Computing Center, University of Erlangen-Nuremberg, Germany
Gerhard Wellein , Erlangen Regional Computing Center, University of Erlangen-Nuremberg, Germany
ABSTRACT
Classic vector systems have all but vanished from recent TOP500 lists. Looking at the newly introduced NEC SX-9 series, we benchmark its memory subsystem using the low level vector triad and employ an advanced lattice Boltzmann flow solver kernel to demonstrate that classic vectors still combine excellent performance with a well-established optimization approach. Results for commodity x86-based systems are provided for reference.
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CITATION

G. Hager, T. Zeiser and G. Wellein, "The world's fastest CPU and SMP node: Some performance results from the NEC SX-9," 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), Rome, 2009, pp. 1-8.
doi:10.1109/IPDPS.2009.5161089
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