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Parallel and Distributed Processing Symposium, International (2009)
Rome, Italy
May 23, 2009 to May 29, 2009
ISBN: 978-1-4244-3751-1
pp: 1-11
Vikas Aggarwal , IBM India Research Lab, Plot 4, Block C, Vasant Kunj Inst. Area, New Delhi 110070, India
Yogish Sabharwal , IBM India Research Lab, Plot 4, Block C, Vasant Kunj Inst. Area, New Delhi 110070, India
Rahul Garg , IBM India Research Lab, Plot 4, Block C, Vasant Kunj Inst. Area, New Delhi 110070, India
Philip Heidelberger , IBM T. J. Watson Research Center, 1101 Kitchawan Rd, Rt. 134, Yorktown Heights, NY 10598, USA
ABSTRACT
In this paper we examine the key elements determining the performance of the HPC Challenge RandomAccess benchmark on next generation supercomputers. We find that the performance of this benchmark is closely related to the bisection bandwidth of the underlying communication network, performance of integer divide operation and details of benchmark specifications such as error tolerance and permissible multi-core mapping strategies. We demonstrate that seemingly small and innocuous changes in the benchmark can lead to significantly different system performance. We also present an algorithm to optimize RandomAccess benchmark for multi-core systems. Our algorithm uses aggregation and software routing and balances the load on the cores by specializing each of the cores for one specific routing or update function. This algorithm gives approximately a factor of 3 speedup on the Blue Gene/P system which is based on quad-core nodes.
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CITATION

Y. Sabharwal, R. Garg, P. Heidelberger and V. Aggarwal, "HPCC RandomAccess benchmark for next generation supercomputers," 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), Rome, 2009, pp. 1-11.
doi:10.1109/IPDPS.2009.5161019
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