Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
Minoru Watanabe , Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Jyohoku, Hamamatsu, 432-8561, Japan
Mao Nakajima , Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Jyohoku, Hamamatsu, 432-8561, Japan
Daisaku Seto , Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Jyohoku, Hamamatsu, 432-8561, Japan
Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However, in ORGAs, although a large virtual gate count can be realized by exploiting the large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, although only a 1.83–1.89 ms single-context holographic configuration and a retention time of 3.49−5.61 s of DORGA architecture have been confirmed, the performance at nanosecond-scale reconfiguration with a multi-context DORGA architecture has never been analyzed. Therefore, this paper presents the experimental result of a 937.5 ns multi-context holographic configuration and a 30.75 μs retention time of DORGA architecture. The advantages of this architecture are discussed in relation to the results of this study.
Minoru Watanabe, Mao Nakajima, Daisaku Seto, "A 937.5 ns multi-context holographic configuration with a 30.75 µs retention time", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-6, 2008, doi:10.1109/IPDPS.2008.4536539