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Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-5
Kensaku Yamashita , Graduate School of Information Sciences, Tohoku University, Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan
Michitaka Kameyama , Graduate School of Information Sciences, Tohoku University, Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan
Masanori Hariyama , Graduate School of Information Sciences, Tohoku University, Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan
ABSTRACT
This paper presents a vehicle detection algorithm using 3-dimensional(3-D) information and its FPGA implementation. For high-speed acquisition of 3-D information, feature-based stereo matching is employed to reduce search area. Our algorithm consists of some tasks with high degree of column-level parallelism. Based on the parallelism, we propose area-efficient VLSI architecture with local data transfer between memory modules and processing elements. Images are equally divided into blocks with some columns, and a block is allocated to a PE. Each PE performs the processing in parallel. The proposed architecture is implemented on FPGA (Altera Stratix EP1S40F1020C7). For specifications of image size 640×480, 100 frames/sec, and operating frequency 100MHz, only 11,000 logic elements (≪ 30%) are required for 30PEs.
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CITATION
Kensaku Yamashita, Michitaka Kameyama, Masanori Hariyama, "FPGA implementation of a vehicle detection algorithm using three-dimensional information", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-5, 2008, doi:10.1109/IPDPS.2008.4536535
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