Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
Kenneth L. Rice , Department of Electrical and Computer Engineering, Clemson University, SC 29634, USA
Tarek M. Taha , Department of Electrical and Computer Engineering, Clemson University, SC 29634, USA
Christopher N. Vutsinas , Department of Electrical and Computer Engineering, Clemson University, SC 29634, USA
In this paper we study the acceleration of a new class of cognitive processing applications based on the structure of the neocortex. Our focus is on a model of the visual cortex used for image recognition developed by George and Hawkins. We propose techniques to accelerate the algorithm using reconfigurable logic, specifically a streaming memory architecture utilizing available off-chip memory. We discuss the design of a streaming memory access unit enabling a large number of processing elements to be placed on a single FPGA thus increasing throughput. We present an implementation of our approach on a Cray XD1 and discuss possible extensions to further increase throughput. Our results indicate that using a two FPGA design with streaming memory gives a speedup of 71.9 times over a purely software implementation.
Kenneth L. Rice, Tarek M. Taha, Christopher N. Vutsinas, "A neocortex model implementation on reconfigurable logic with streaming memory", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-8, 2008, doi:10.1109/IPDPS.2008.4536533