The Community for Technology Leaders
Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-8
Rabi N. Mahapatra , Embedded Systems and Co-Design Group, Dept. of Computer Science, Texas A&M University, College Station, 77843, USA
Yoonjin Kim , Embedded Systems and Co-Design Group, Dept. of Computer Science, Texas A&M University, College Station, 77843, USA
ABSTRACT
Coarse-grained reconfigurable architectures (CGRA) require many processing elements and a configuration memory unit (configuration cache) for reconfiguration of the ALU array elements. This structure consumes significant amount of power. Power reduction during reconfiguration is necessary for the reconfigurable architecture to be used as a competitive IP core in embedded systems. In this paper, we propose a power-conscious reusable context pipelining architecture for CGRA that efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves up to 57.97% of the total power consumed in the configuration cache with reduced configuration cache size compared to the previous approach.
INDEX TERMS
CITATION
Rabi N. Mahapatra, Yoonjin Kim, "Reusable context pipelining for low power coarse-grained reconfigurable architecture", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-8, 2008, doi:10.1109/IPDPS.2008.4536523
109 ms
(Ver 3.3 (11022016))