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Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-8
Viktor Owall , Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00, Sweden
Thomas Lenart , Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00, Sweden
Henrik Svensson , Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00, Sweden
ABSTRACT
This paper presents a coarse-grained reconfigurable architecture based on an array of processing and memory cells. Memory cells are distributed and placed close to processing cells to reduce memory bottlenecks. Processing cells are instruction set processors with enhanced performance for communication-intensive inner loops. Processor communication is performed using a self-synchronizing protocol that simplifies algorithm mapping and manages unpredictable time variations. The reconfigurable architecture is described as a scalable and parameterizable SystemC transaction level model, which allows rapid architectural exploration. Our exploration environment SCENIC is used to setup scenarios, control the simulation models and to extract performance data during simulation. A case study demonstrates different implementations of a filter algorithm, and how exploration is used to tune and optimize for execution time, latency, or used resources.
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CITATION
Viktor Owall, Thomas Lenart, Henrik Svensson, "Modelling and exploration of a reconfigurable array using systemC TLM", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-8, 2008, doi:10.1109/IPDPS.2008.4536521
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