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Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-6
Jurgen Becker , ITIV, Universität Karlsruhe (TH), Germany
Lars Braun , ITIV, Universität Karlsruhe (TH), Germany
Diana Gohringer , FGAN-FOM, Ettlingen Karlsruhe, Germany
Michael Hubner , ITIV, Universität Karlsruhe (TH), Germany
Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These Systems-on-Chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called Network-on-Chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer Network-on-Chip and the related techniques for adapting the network while run-time to the requirements of an application.
Jurgen Becker, Lars Braun, Diana Gohringer, Michael Hubner, "Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems", Parallel and Distributed Processing Symposium, International, vol. 00, no. , pp. 1-6, 2008, doi:10.1109/IPDPS.2008.4536504
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