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Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-10
Aditya Yanamandra , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Bryan Cover , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Padma Raghavan , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Mary Jane Irwin , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Mahmut Kandemir , Department of Computer Science and Engineering, The Pennsylvania State University, USA
ABSTRACT
Scratchpad memories (SPMs) have been shown to be more energy efficient and have faster access times than traditional hardware-managed caches. This, coupled with the predictability of data presence, makes SPMs an attractive alternative to cache for many scientific applications. In this work, we consider an SPM based system for increasing the performance and the energy efficiency of sparse matrix-vector multiplication on a chip multi-processor. We ensure the efficient utilization of the SPM by profiling the application for the data structures which do not perform well in traditional cache. We evaluate the impact of using an SPM at all levels of the on-chip memory hierarchy. Our experimental results show an average increase in performance by 13.5-15% and an average decrease in the energy consumption by 28-33% on an 8-core system depending on which level of the hierarchy the SPM is utilized.
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CITATION

M. J. Irwin, M. Kandemir, A. Yanamandra, B. Cover and P. Raghavan, "Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations," 2008 IEEE International Parallel & Distributed Processing Symposium(IPDPS), Miami, FL, 2008, pp. 1-10.
doi:10.1109/IPDPS.2008.4536314
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