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Parallel and Distributed Processing Symposium, International (2008)
Miami, FL, USA
Apr. 14, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-1693-6
pp: 1-8
Yuto Hosogaya , Tokyo Institute of Technology, Japan
Toshio Endo , Tokyo Institute of Technology, Japan
Satoshi Matsuoka , Tokyo Institute of Technology, Japan
ABSTRACT
With increasing demand for low power high performance computing, reducing power of not only CPUs but also memory is becoming important. In typical general-purpose HPC environments, DRAM is installed in an over-provisioned fashion to avoid swapping, although in most cases not all such memory is used, leading to unnecessary and excessive power consumption, even in a standby state. We propose a next generation low power memory system that reduces required DRAM capacity while minimizing application performance degradation. In this system, both DRAM and MRAM, fast non-volatile memory, are used as main memory, while flash memory is used as a swap device. Our profile-based paging algorithm optimizes memory accesses by using faster memory as much as possible, reducing accesses to slower memory. Simulated results of our architecture show that the overall energy consumption of the memory system can be reduced to 25% by in the best case by reducing DRAM capacity, with only 17% performance loss in application benchmarks.
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CITATION

Satoshi Matsuoka, Toshio Endo and Yuto Hosogaya, "Performance evaluation of parallel applications on next generation memory architecture with power-aware paging method," 2008 IEEE International Parallel & Distributed Processing Symposium(IPDPS), Miami, FL, 2008, pp. 1-8.
doi:10.1109/IPDPS.2008.4536222
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