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Parallel and Distributed Processing Symposium, International (2007)
Long Beach, CA, USA
Mar. 26, 2007 to Mar. 30, 2007
ISBN: 1-4244-0909-8
pp: 494
Michel Dubois , University of Southern California, Dept. of Electrical Engineering, Los Angeles, CA 90089-2562, USA. dubois@paris.usc.edu
Hyunyoung Lee , University of Denver, Dept. of Computer Science, Denver, CO 80208, USA. hlee@cs.du.edu
Lan Lin , University of Denver, Dept. of Computer Science, Denver, CO 80208, USA. llin@cs.du.edu
ABSTRACT
We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous Multi-Processing) as a universal performance and power complexity model for multithreaded algorithms and systems. We provide examples to illustrate how to design and analyze algorithms using STAMP and how to apply the complexity estimates to better utilize CMP(Chip MultiProcessor)-based machines within given constraints such as power.
INDEX TERMS
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CITATION

L. Lin, H. Lee and M. Dubois, "STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems," 2007 IEEE International Parallel and Distributed Processing Symposium(IPDPS), Rome, 2007, pp. 494.
doi:10.1109/IPDPS.2007.370684
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