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Parallel and Distributed Processing Symposium, International (2006)
Rhodes Island, Greece
Apr. 25, 2006 to Apr. 29, 2006
ISBN: 1-4244-0054-6
pp: 339
Seung Woo Son , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA, USA
K. Malkowski , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA, USA
Guilin Chen , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA, USA
P. Raghavan , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA, USA
ABSTRACT
Reducing power consumption is quickly becoming a first-class optimization metric for many high-performance parallel computing platforms. One of the techniques employed by many prior proposals along this direction is voltage scaling and past research used it on different components such as networks, CPUs, and memories. In contrast to most of the existent efforts on voltage scaling that target a single component (CPU, network or memory components), this paper proposes and experimentally evaluates a voltage/frequency scaling algorithm that considers CPU and communication links in a mesh network at the same time. More specifically, it scales voltages/frequencies of both CPUs in the network and the communication links among them in a coordinated fashion (instead of one after another) such that energy savings are maximized without impacting execution time. Our experiments with several tree-based sparse matrix computations reveal that the proposed integrated voltage scaling approach is very effective in practice and brings 13% and 17% energy savings over the pure CPU and pure communication link voltage scaling schemes, respectively. The results also show that our savings are consistent with the different network sizes and different sets of voltage/frequency levels.
INDEX TERMS
frequency scaling, integrated link/CPU voltage scaling, energy consumption, parallel sparse matrix application, optimization metric, high-performance parallel computing
CITATION

M. Kandemir, P. Raghavan, Guilin Chen, K. Malkowski and Seung Woo Son, "Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications," Parallel and Distributed Processing Symposium, International(IPDPS), Rhodes Island, Greece, 2006, pp. 339.
doi:10.1109/IPDPS.2006.1639596
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