The Community for Technology Leaders
Parallel and Distributed Processing Symposium, International (2006)
Rhodes Island, Greece
Apr. 25, 2006 to Apr. 29, 2006
ISBN: 1-4244-0054-6
pp: 60
P. de Langen , Fac. of Electr. Eng., Math.&Comput. Sci., Delft Univ. of Technol., Netherlands
B. Juurlink , Fac. of Electr. Eng., Math.&Comput. Sci., Delft Univ. of Technol., Netherlands
ABSTRACT
It is expected that (single chip) multiprocessors will increasingly be deployed to realize high-performance embedded systems. Because in current technologies the dynamic power consumption dominates the static power dissipation, an effective technique to reduce energy consumption is to employ as many processors as possible in order to finish the tasks as early as possible, and to use the remaining time before the deadline (the slack) to apply voltage scaling. We refer to this heuristic as schedule and stretch (S&S). However, since the static power consumption is expected to become more significant, this approach is no longer efficient when leakage current is taken into account. In this paper, we first show for which combinations of leakage current, supply voltage, and clock frequency the static power consumption dominates the dynamic power dissipation. These results imply that, at a certain point, it is no longer advantageous from an energy perspective to employ as many processors as possible. Thereafter, a heuristic is presented to schedule the tasks on a number of processors that minimizes the total energy consumption. Experimental results obtained using a public task graph benchmark set show that our leakage-aware scheduling algorithm reduces the total energy consumption by up to 24% for tight deadlines (1.5/spl times/ the critical path length) and by up to 67% for loose deadlines (8/spl times/ the critical path length) compared to S&S.
INDEX TERMS
public task graph benchmark set, leakage-aware multiprocessor scheduling, single chip multiprocessor, energy consumption, voltage scaling, schedule and stretch, leakage current, supply voltage, clock frequency, static power consumption, power dissipation
CITATION

P. de Langen and B. Juurlink, "Leakage-aware multiprocessor scheduling for low power," Parallel and Distributed Processing Symposium, International(IPDPS), Rhodes Island, Greece, 2006, pp. 60.
doi:10.1109/IPDPS.2006.1639317
140 ms
(Ver 3.3 (11022016))