CSDL Home I IPDPS 2005 Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium
April 4, 2005 to April 8, 2005
Ramakrishna Kotla , University of Texas at Austin
Soraya Ghiasi , IBM Austin Research Laboratory
Tom Keller , IBM Austin Research Laboratory
Freeman Rawson , IBM Austin Research Laboratory
Modern server farm and cluster sites consume large quantities of energy both to power and cool the machines in the site. At the same time, less power supply redundancy is offered and power companies and government officials are requesting power consumption be reduced during certain time periods. These trends lead to the requirement of responding to rapid reductions in the maximum power the site may consume. Each possible solution must respond to the new power budget before a cascading failure occurs. Available techniques include powering down some nodes or slowing all nodes in a system uniformly. This work instead examines the feasibility of slowing nodes non-uniformly in response to their performance demands. This approach provides an opportunity to reduce the performance loss caused by a reduction in the power budget.<div></div> This paper uses the execution characteristics of the work currently running on each processor of the system or cluster to predict the performance of the work at the available frequency settings. The scheduling mechanism selects the lowest frequency for the processor that provides essentially all of the available performance of the work. It ensures that the frequency fits within the available global power budget and, if not, reduces it so that it does. The paper demonstrates the approach using a simple, synthetic benchmark and then validates it using additional, real-world applications.
Ramakrishna Kotla, Soraya Ghiasi, Tom Keller, Freeman Rawson, "Scheduling Processor Voltage and Frequency in Server and Cluster Systems", IPDPS, 2005, Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium, Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium 2005, pp. 234b, doi:10.1109/IPDPS.2005.392