The Community for Technology Leaders
Parallel and Distributed Processing Symposium, International (2005)
Denver, Colorado
Apr. 4, 2005 to Apr. 8, 2005
ISSN: 1530-2075
ISBN: 0-7695-2312-9
TABLE OF CONTENTS
Reconfigurable Architecture Workshop - RAW

Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory (Abstract)

Sho Ogata , Tohoku University, Japan
Michitaka Kameyama , Tohoku University, Japan
Masanori Hariyama , Tohoku University, Japan
Weisheng Chong , Tohoku University, Japan
pp. 144a

Hardware Based Online Profiling in AMIDAR Processors (Abstract)

Stephan Gatzka , Dresden University of Technology, Germany
Christian Hochberger , Dresden University of Technology, Germany
pp. 144b

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit (Abstract)

Minoru Watanabe , Kyushu Institute of Technology, Japan
Fuminori Kobayashi , Kyushu Institute of Technology, Japan
pp. 145a

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA (Abstract)

Mukesh Chugh , University of Texas at Dallas
Poras T. Balsara , University of Texas at Dallas
Dinesh Bhatia , University of Texas at Dallas
pp. 145b

Power Quality Disturbance Detection Using Artificial Intelligence: A Hardware Approach (Abstract)

F. Choong , Multimedia University, Cyberjaya, Malaysia
M. B. I. Reaz , Multimedia University, Cyberjaya, Malaysia
F. Mohd-Yasin , Multimedia University, Cyberjaya, Malaysia
pp. 146a

FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic (Abstract)

Owen Callanan , Trinity College, Dublin, Ireland
David Gregg , Trinity College, Dublin, Ireland
Emre ?zer , Trinity College, Dublin, Ireland
Andy Nisbet , Manchester Metropolitan University, UK
James Sexton , Trinity College, Dublin
pp. 146b

Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores (Abstract)

Gerald R. Morris , University of Southern California, Los Angeles
Viktor K. Prasanna , University of Southern California, Los Angeles
Ling Zhuo , University of Southern California, Los Angeles
pp. 147a

A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms (Abstract)

Sami Khawam , The University of Edinburgh, UK
Tony Kirkham , EPSON Scotland Design Centre, UK
Konstantinos Katsoulakis , The University of Edinburgh, UK
Tughrul Arslan , The University of Edinburgh, UK; Institute for System Level Integration, UK
pp. 147b

MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors (Abstract)

Viktor K. Prasanna , University of Southern California, Los Angeles
Jingzhao Ou , University of Southern California, Los Angeles
pp. 148b

Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores (Abstract)

J?rgen Becker , Universitaet Karlsruhe (TH), Germany
Katarina Paulsson , Universitaet Karlsruhe (TH), Germany
Michael H? , Universitaet Karlsruhe (TH), Germany
pp. 149a

Hardware-Software Interaction: Preliminary Observations (Abstract)

Neil Steiner , Virginia Polytechnic Institute and State University, Blacksburg, VA
Peter Athanas , Virginia Polytechnic Institute and State University, Blacksburg, VA
pp. 149b

Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems (Abstract)

C. Debaes , Vrije Universiteit Brussel, TONA, Belgium
J. Van Campenhout , Universiteit Gent, ELIS, Belgium
H. Thienpont , Vrije Universiteit Brussel, TONA, Belgium
J. Dambre , Universiteit Gent, ELIS, Belgium
W. Heirman , Universiteit Gent, ELIS, Belgium
pp. 150a

Quick Reconfiguration in Clustered Micro-Sequencer (Abstract)

Seda Ogrenci Memik , Northwestern University, Evanston, IL
Majid Sarrafzadeh , UCLA, Los Angeles, CA
Roozbeh Jafari , UCLA, Los Angeles, CA
pp. 150b

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching (Abstract)

Markus Rullmann , Dresden University of Technology, Germany
Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
pp. 151a

REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems (Abstract)

H. Kalte , University of Western Australia, Crawley WA
G. Lee , University of Western Australia, Crawley WA
M. Porrmann , University of Paderborn, Germany
U. R?ckert , University of Paderborn, Germany
pp. 151b

A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection (Abstract)

Tatsuo Hiramatsu , SANYO Electric Co., Ltd., Japan
Makoto Ozone , SANYO Electric Co., Ltd., Japan
Shinji Kimura , Waseda University, Japan
Makoto Okada , SANYO Electric Co., Ltd., Japan
Hiroshi Nakajima , SANYO Electric Co., Ltd., Japan
Katsunori Hirase , SANYO Electric Co., Ltd., Japan
pp. 152a

Configuration Steering for a Reconfigurable Superscalar Processor (Abstract)

Monte P. Tull , University of Oklahoma
John K. Antonio , University of Oklahoma
Brian F. Veale , University of Oklahoma
pp. 152b

A Master-Slave Adaptive Load-Distribution Processor Model on PCA (Abstract)

Junji Kitamichi , The Univ. of Aizu, Japan
Toshiyuki Ito , The Univ. of Aizu, Japan
Kenichi Kuroda , The Univ. of Aizu, Japan
Yuichi Okuyama , NTT Network Innovation Lab., Japan
pp. 153a

Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms (Abstract)

David Andrews , University of Kansas
John Gauch , University of Kansas
Wesley Peck , University of Kansas
Dan Chirpich , University of Kansas
Kevin Stout , University of Kansas
Razali Jidin , University of Kansas
pp. 153b

A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems (Abstract)

Paulo R. M. Maciel , Federal University of Pernambuco
Carlos A. Valderrama , Federal University of Pernambuco
Paulo S. B. Nascimento , Federal University of Pernambuco
Abel G. S. Filho , Federal University of Pernambuco
Remy Eskinazi , University of the State of Pernambuco
Manoel E. Lima , Federal University of Pernambuco
pp. 154a

Packet Routing in Dynamically Changing Networks on Chip (Abstract)

Mateusz Majer , University of Erlangen-Nuremberg, Germany
J? Teich , University of Erlangen-Nuremberg, Germany
Christophe Bobda , University of Erlangen-Nuremberg, Germany
Ali Ahmadinia , University of Erlangen-Nuremberg, Germany
pp. 154b

An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip (Abstract)

Gerard J. M. Smit , University of Twente, The Netherlands
Gerard K. Rauwerda , University of Twente, The Netherlands
Pascal T. Wolkotte , University of Twente, The Netherlands
Lodewijk T. Smit , University of Twente, The Netherlands
pp. 155a

Hardware Enhanced Function Allocation Management in Reconfigurable Systems (Abstract)

J?rgen Becker , Universit?t Karlsruhe (TH), Germany
Wansheng Jin , Universit?t Karlsruhe (TH), Germany
Michael Ullmann , Universit?t Karlsruhe (TH), Germany
pp. 156a

Application of Binary Translation to Java Reconfigurable Architectures (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Antonio C. S. Beck , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 156b

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms (Abstract)

C. E. Goutis , University of Patras, Rio, Greece
M. D. Galanis , University of Patras, Rio, Greece
D. Soudris , Democritus University, Xanthi, Greece
A. Milidonis , University of Patras, Rio, Greece
G. Theodoridis , Aristotle University, Thessalonica, Greece
pp. 157a

Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis (Abstract)

Jeffery S. Vetter , Oak Ridge National Laboratory, TN
Xuejun Liang , Jackson State University
Melissa C. Smith , Oak Ridge National Laboratory, TN
pp. 157b

IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application (Abstract)

John Lockwood , Washington University, St. Louis, MO
Jing Lu , Washington University, St. Louis, MO
pp. 158b

Bandwidth Management with a Reconfigurable Data Cache (Abstract)

Pradeep Nalabalapu , Ambarella Corp., Sunnyvale, CA
Ron Sass , ITTC / University of Kansas, Lawrence, KS
pp. 159a

Design and Implementation of an Efficient Stack Machine (Abstract)

Martin Schoeberl , JOP.design, Vienna, Austria
pp. 159b

A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture (Abstract)

M. Ferri , ARCES, Universit? di Bologna
C. Mucci , ARCES, Universit? di Bologna
F. Campi , Central R&D STMicroelectronic
M. Bocchi , ARCES, Universit? di Bologna
A. Fazzi , ARCES, Universit? di Bologna
A. Deledda , ARCES, Universit? di Bologna
pp. 160a

A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures (Abstract)

C. E. Goutis , University of Patras, Greece
G. Dimitroulakos , University of Patras, Greece
M. D. Galanis , University of Patras, Greece
pp. 160b

Domain-Specific Reconfigurable Array Targeting Discrete Wavelet Transform for System-on-Chip Applications (Abstract)

Sajid Baloch , University of Edinburgh, UK; Institute for System Level Integration, UK
Imran Ahmed , University of Edinburgh, UK; Institute for System Level Integration, UK
Tughrul Arslan , University of Edinburgh, UK; Institute for System Level Integration, UK
pp. 161a

A Low-Cost Realization of an Adaptable Protocol Processing Unit (Abstract)

Alex Gleich , Fraunhofer IIS / EAS Dresden, Germany
Maik Boden , Fraunhofer IIS / EAS Dresden, Germany
Steffen R? , Fraunhofer IIS / EAS Dresden, Germany
Ulrich Nageldinger , Infineon Technologies AG, Germany
pp. 161b

Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems (Abstract)

M. Kandemir , Pennsylvania State University
U. Sezer , University of Wisconsin
G. Chen , Pennsylvania State University
S. Tosun , Syracuse University
pp. 162a

Reconfigurable Sequential Consistency Algorithm (Abstract)

Carlos A. P. S. Martins , Pontifical Catholic University of Minas Gerais, Brazil
Lu?s F. W. G? , Pontifical Catholic University of Minas Gerais, Brazil
Dulcin?ia O. Da Penha , Pontifical Catholic University of Minas Gerais, Brazil
Christiane V. Pousa , Pontifical Catholic University of Minas Gerais, Brazil
pp. 162b

Generic Design Space Exploration for Reconfigurable Architectures (Abstract)

Lilian Bossuet , Universit? de Bretagne Sud, Lorient, France
Jean-Luc Philippe , Universit? de Bretagne Sud, Lorient, France
Guy Gogniat , Universit? de Bretagne Sud, Lorient, France
pp. 163a

A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture (Abstract)

Donatella Sciuto , Politecnico di Milano, Italy
Marco D. Santambrogio , Politecnico di Milano, Italy
Fabrizio Ferrandi , Politecnico di Milano, Italy
pp. 163b

Reconfigurable Address Generators for Stream-Based Computation Implemented on FPGAs (Abstract)

Kjetil E. Vistnes , University of Oslo, Norway
Oddvar S?r?sen , University of Oslo, Norway
pp. 164a

Placement-Oriented Modeling of Partially Reconfigurable Architectures (Abstract)

Markus Koester , University of Paderborn, Germany
Ulrich R?ckert , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
pp. 164b

Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer (Abstract)

Miguel M. Silva , FEUP/DEEC, Portugal
Jo?o Canas Ferreira , FEUP/DEEC and INESC Porto, Portugal
pp. 165a

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation (Abstract)

G. Koutroumpezis , Democritus University of Thrace, Greece
D. Soudris , Democritus University of Thrace, Greece
K. Siozios , Democritus University of Thrace, Greece
K. Tatas , Democritus University of Thrace, Greece
A. Thanailakis , Democritus University of Thrace, Greece
pp. 165b

IP Lookup on a Platform FPGA: A Comparative Study (Abstract)

Dennis Bemmann , Humboldt University, Berlin, Germany
pp. 166a

Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication (Abstract)

Robin Woodburn , MED Ltd., UK
Ian Underwood , MED Ltd., UK
Sajid Baloch , University of Edinburgh, UK; Institute for System Level Integration, UK; MED Ltd., UK
Tughrul Arslan , University of Edinburgh, UK; Institute for System Level Integration, UK
Imran Ahmed , University of Edinburgh, UK; Institute for System Level Integration, UK; MED Ltd., UK
pp. 166b

An FPGA-Based, Multi-model Simulation Method for Biochemical Systems (Abstract)

Hiroaki Kitano , ERATO-SORST, JST, Japan
Tomonori Fukushima , Keio University, Yokohama, Japan
Noriko Hiroi , ERATO-SORST, JST, Japan
Yow Iwaoka , Keio University, Yokohama, Japan
Yuichiro Shibata , Nagasaki University, Japan
Yasunori Osana , Keio University, Yokohama, Japan
Hideharu Amano , Keio University, Japan
Akira Funahashi , ERATO-SORST, JST, Japan
Masato Yoshimi , Keio University, Yokohama, Japan
pp. 167a

Experiences with Soft-Core Processor Design (Abstract)

Zvonko G. Vranesic , University of Toronto, Canada
Franjo Plavec , University of Toronto, Canada
Stephen D. Brown , University of Toronto, Canada
Blair Fort , University of Toronto, Canada
pp. 167b

Analysis of Hardware Acceleration in Reconfigurable Embedded Systems (Abstract)

Matthew Ouellette , Xilinx, Inc.
Dan Connors , University of Colorado, Boulder
pp. 168a

A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications (Abstract)

Tughrul Arslan , University of Edinburgh, UK; Institute for System Level Integration, UK
Yutian Zhao , University of Edinburgh, UK
Ahmet T. Erdogan , University of Edinburgh, UK; Institute for System Level Integration, UK
pp. 169a

Programming Configurable Multiprocessors (Abstract)

Steven A. Guccione , Cmpware, Inc., Austin, TX
pp. 169b

Embedded MPLS Architecture (Abstract)

Raymond Peterkin , University of Ottawa, Canada
Dan Ionescu , University of Ottawa, Canada
pp. 170a

An FPGA Based Test Bed for Bio Inspired Computation (Abstract)

Kolin Paul , Indian Institute of Technology Delhi
pp. 170b

Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip (Abstract)

Stefan Zink , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
Heiko Zimmer , Darmstadt University of Technology
Thomas Hollstein , Darmstadt University of Technology
pp. 171a

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures (Abstract)

F. Rivera , Universidad Complutense, Spain
M. Sanchez-Elez , Universidad Complutense, Spain
N. Bagherzadeh , University of California, Irvine
R. Hermida , Universidad Complutense, Spain
M. Fernandez , Universidad Complutense, Spain
pp. 171b

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs (Abstract)

Vikram Chandrasekhar , Indian Institute of Technology Madras, Chennai, India
M. Sashikanth , Indian Institute of Technology Madras, Chennai, India
V. Kamakoti , Indian Institute of Technology Madras, Chennai, India
E. Syam Sundar Reddy , Indian Institute of Technology Madras, Chennai, India
N. Vijaykrishnan , Pennsylvania State University, USA
pp. 172a

Dynamic Reconfiguration of Mechatronic Real-Time Systems Based on Configuration State Machines (Abstract)

Roland Kasper , University Magdeburg, Germany
Thomas Reinemann , University Magdeburg, Germany
Steffen Toscher , University Magdeburg, Germany
pp. 172b
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