CSDL Home I IPDPS 2005 Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium
April 4, 2005 to April 8, 2005
Brian F. Veale , University of Oklahoma
John K. Antonio , University of Oklahoma
Monte P. Tull , University of Oklahoma
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration of the processor is defined according to how its reconfigurable execution units are configured. An efficient micro-architectural solution to configuration management is presented that effectively steers the current processor configuration toward a configuration that is well matched with the execution unit requirements of instructions being scheduled for execution. The approach first selects the best matched among four steering configurations based on the number and type of execution units required by the instructions. One of the steering configurations is dynamically defined as the current configuration; the other three are statically predefined. Once a steering configuration is selected, portions of it begin loading on corresponding reconfigurable execution units that are not busy. The active configuration of the processor is generally the overlap of two or more steering configurations.
Brian F. Veale, John K. Antonio, Monte P. Tull, "Configuration Steering for a Reconfigurable Superscalar Processor", IPDPS, 2005, Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium, Proceedings. 19th IEEE International Parallel and Distributed Processing Symposium 2005, pp. 152b, doi:10.1109/IPDPS.2005.148