Parallel and Distributed Processing Symposium, International (2005)
Apr. 4, 2005 to Apr. 8, 2005
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.64
Makoto Okada , SANYO Electric Co., Ltd., Japan
Tatsuo Hiramatsu , SANYO Electric Co., Ltd., Japan
Hiroshi Nakajima , SANYO Electric Co., Ltd., Japan
Makoto Ozone , SANYO Electric Co., Ltd., Japan
Katsunori Hirase , SANYO Electric Co., Ltd., Japan
Shinji Kimura , Waseda University, Japan
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.
T. Hiramatsu, M. Ozone, S. Kimura, M. Okada, H. Nakajima and K. Hirase, "A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection," 19th IEEE International Parallel and Distributed Processing Symposium(IPDPS), Denver, CO, 2005, pp. 152a.