The Community for Technology Leaders
Parallel and Distributed Processing Symposium, International (2004)
Santa Fe, New Mexico
Apr. 26, 2004 to Apr. 30, 2004
ISBN: 0-7695-2132-0
TABLE OF CONTENTS
Introduction
Papers

Of Gates and Wires (Abstract)

Patrick Lysaght , Xilinx Research Labs
Delon Levi , Xilinx Research Labs
pp. 132a

A Parallel Architecture for Secure FPGA Symmetric Encryption (Abstract)

E. J. Swankoski , Applied Research Laboratory
M. Kandemir , Pennsylvania State University
V. Narayanan , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
pp. 132b

Tuning Reconfigurable Microarchitectures for Power Efficiency (Abstract)

James E. Smith , University of Wisconsin-Madison
Ashutosh S. Dhodapkar , University of Wisconsin-Madison
pp. 133a

A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling (Abstract)

S. Sezer , Queen?s University Belfast
E. Garcia , Queen?s University Belfast
V. Stewart , Queen?s University Belfast
C. Toal , Queen?s University Belfast
pp. 133b

A New Approach for On-line Placement on Reconfigurable Devices (Abstract)

Jürgen Teich , University of Erlangen-Nuremberg
Ali Ahmadinia , University of Erlangen-Nuremberg
Marcus Bednara , University of Erlangen-Nuremberg
Christophe Bobda , University of Erlangen-Nuremberg
pp. 134a

Improving Java Performance Using Dynamic Method Migration on FPGAs (Abstract)

Mahmuth Kandemir , Penn State University
Vijaykrishnan Narayanan , Penn State University
Alessandro Bogliolo , University of Urbino
Aman Gayasen , Penn State University
Emanuele Lattanzi , University of Urbino
Luca Benini , University of Bologna
pp. 134b

An FPGA Run-Time System for Dynamical On-Demand Reconfiguration (Abstract)

J? Becker , Universit?t Karlsruhe
Michael H? , Universit?t Karlsruhe
Bj? Grimm , Universit?t Karlsruhe
Michael Ullmann , Universit?t Karlsruhe
pp. 135a

Runtime Reconfigurable Interfaces — The RTR-IFB Approach (Abstract)

Wolfram Hardt , Chemnitz University of Technology
Stefan Ihmor , University of Paderborn
pp. 136a

System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications (Abstract)

Mohamed Taher , The George Washington University
Nikitas Alexandridis , The George Washington University
Tarek El-Ghazawi , The George Washington University
David Caliga , SRC Computers
Kris Gaj , George Mason University
Esam El-Araby , The George Washington University
pp. 136b

Embedded Software Integration for Coarse-Grain Reconfigurable Systems (Abstract)

Patrick Schaumont , University of California at Los Angeles
Alireza Hodjat , University of California at Los Angeles
Kazuo Sakiyama , University of California at Los Angeles
Ingrid Verbauwhede , University of California at Los Angeles
pp. 137

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development (Abstract)

A. Thanailakis , Democritus University of Thrace
K. Tatas , Democritus University of Thrace
G. Koytroympezis , Democritus University of Thrace
V. Kalenteridis , Aristotle University of Thessaloniki
H. Pournara , Aristotle University of Thessaloniki
S. Siskos , Aristotle University of Thessaloniki
S. Nikolaidis , Aristotle University of Thessaloniki
K. Siozios , Democritus University of Thrace
D. J. Soudris , Democritus University of Thrace
I. Pappas , Aristotle University of Thessaloniki
pp. 138a

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration (Abstract)

Juergen Becker , Universitaet Karlsruhe
Florian Weissel , Universitaet Karlsruhe
Michael Huebner , Universitaet Karlsruhe
Michael Ullmann , Universitaet Karlsruhe
pp. 138b

Integrated Modeling and Generation of a Reconfigurable Network-on-Chip (Abstract)

Patrick Schaumont , University of California at Los Angeles
Ingrid Verbauwhede , University of California at Los Angeles
Doris Ching , University of California at Los Angeles
pp. 139b

Hardware Assisted Two Dimensional Ultra Fast Placement (Abstract)

Manish Handa , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 140b

System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement (Abstract)

M. Porrmann , University of Paderborn
H. Kalte , University of Paderborn
U. R?ckert , University of Paderborn
pp. 141a

Non-Contiguous Linear Placement for Reconfigurable Fabrics (Abstract)

Kia Bazargan , University of Minnesota
Cristinel Ababei , University of Minnesota
pp. 141b

Impacting Education Using FPGAs (Abstract)

Don Bouldin , University of Tennessee
pp. 142a

Developing Large-Scale Field-Programmable Analog Arrays (Abstract)

David V. Anderson , Georgia Institute of Technology
Paul Hasler , Georgia Institute of Technology
Tyson S. Hall , Georgia Institute of Technology
Christopher M. Twigg , Georgia Institute of Technology
pp. 142b

Designing a Runtime Reconfigurable Processor for General Purpose Applications (Abstract)

Hans Christoph Zeidler , Universität der Bundeswehr Hamburg
Adronis Niyonkuru , Universität der Bundeswehr Hamburg
pp. 143b

A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2^m) (Abstract)

Arturo Díaz-Pérez , Instituto Politécnico Nacional
Francisco Rodríguez-Henriquez , Instituto Politécnico Nacional
Nazar A. Saqib , Instituto Politécnico Nacional
pp. 144a

Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array (Abstract)

Fabrizio Lombardi , Northeastern University
Jing Huang , Northeastern University
Mehdi B. Tahoori , Northeastern University
pp. 145a

Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs (Abstract)

Michael Wirthlin , Brigham Young University
Paul Graham , Los Alamos National Laboratory
Eric Johnson , Brigham Young University
Maya Gokhale , Los Alamos National Laboratory
Nathan Rollins , Brigham Young University
pp. 145b

Dynamically Configurable Security for SRAM FPGA Bitstreams (Abstract)

Guy Gogniat , Universit? de Bretagne Sud
Wayne Burleson , University of Massachusetts at Amherst
Lilian Bossuet , Universit? de Bretagne Sud
pp. 146a

Adaptive System Architectures (PDF)

Klaus Waldschmidt , J. W. Goethe University
pp. 147a

Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture (Abstract)

Gerard K. Rauwerda , University of Twente
Paul M. Heysters , University of Twente
Gerard J. M. Smit , University of Twente
pp. 147b

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays — Constraints and Methodology (Abstract)

Frank Hannig , University of Erlangen-Nuremberg
Jürgen Teich , University of Erlangen-Nuremberg
Hritam Dutta , University of Erlangen-Nuremberg
pp. 148a

Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing (Abstract)

Gadi Haber , IBM Haifa Research Lab
Daniel Citron , IBM Haifa Research Lab
Yosi Ben-Asher , Haifa University
pp. 148b

A High-Performance and Energy-Efficient Architecture for Floating-Point Based LU Decomposition on FPGAs (Abstract)

Gokul Govindu , University of Southeren California
Viktor Prasanna , University of Southeren California
Sridhar Gangadharpalli , Satyam Computer Services Ltd.
Vikash Daga , Satyam Computer Services Ltd.
Seonil Choi , University of Southeren California
V. Sridhar , Satyam Computer Services Ltd.
pp. 149a

Analysis of High-Performance Floating-Point Arithmetic on FPGAs (Abstract)

Gokul Govindu , University of Southern California
Seonil Choi , University of Southern California
Ling Zhuo , University of Southern California
Viktor Prasanna , University of Southern California
pp. 149b

Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications (Abstract)

Fred Westall , EPSON Scotland Design Centre
Tughrul Arslan , University of Edinburgh and Institute for System Level Integration
Sami Khawam , University of Edinburgh
pp. 150a

Pipelined Multipliers for Reconfigurable Hardware (Abstract)

Mitchell J. Myjak , Washington State University
Jos? G. Delgado-Frias , Washington State University
pp. 150b

Functional Programming for Reconfigurable Computing (Abstract)

Al Strelzoff , Cadence Design Systems
pp. 151a

A Dynamically-Reconfigurable Image Recognition Processor (Abstract)

Leo Karnan , Tohoku University
Koji Kotani , Tohoku University
Naoto Miyamoto , Tohoku University
Kazuyuki Maruo , Advantest Laboratories Ltd.
Masayoshi Ichikawa , Advantest Corporation
Tadahiro Ohmi , Tohoku University
Takahiro Yamaguchi , Advantest Laboratories Ltd.
pp. 151b

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays (Abstract)

B Jayaram , Indian Institute of Technology Madras
V. Kamakoti , Indian Institute of Technology Madras
A. Manoj Kumar , Indian Institute of Technology Madras
R. Manimegalai , Indian Institute of Technology Madras
pp. 152
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