The Community for Technology Leaders
Parallel and Distributed Processing Symposium, International (2000)
Cancun, Mexico
May 1, 2000 to May 5, 2000
ISSN: 1530-2075
ISBN: 0-7695-0574-0
pp: 211
Jason Hiser , University of Virginia
Steve Carr , Michigan Technological University
Philip Sweany , Michigan Technological University
Steven J. Beaty , Metropolitan State College of Denver
ABSTRACT
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations to occur simultaneously at the cost of requiring more registers to hold the operands and results of those operations, and importantly, more ports on the register banks to allow for concurrent access to the data. One approach of ameliorating the number of ports on a register bank (the cost of ports in gates varies as N^2 where N is the number of ports, and adding ports increases access time) is to have multiple register banks with fewer ports, each attached to a subset of the available functional units. This reduces the number of ports needed on a per-bank basis, but can slow operations if a necessary value is not in an attached register bank as copy operations must be inserted. Therefore, there is a circular dependence between assigning operations to functional units and assigning values to register banks. We describe an approach that produces good code by separating partitioning from scheduling and register assignment. Our method is independent of both the scheduling technique and register assignment method used.
INDEX TERMS
CITATION

S. Carr, P. Sweany, S. J. Beaty and J. Hiser, "Register Assignment for Software Pipelining with Partitioned Register Banks," Parallel and Distributed Processing Symposium, International(IPDPS), Cancun, Mexico, 2000, pp. 211.
doi:10.1109/IPDPS.2000.845983
91 ms
(Ver 3.3 (11022016))