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On-Line Testing Workshop, IEEE International (2002)
Isle of Bendor, France
July 8, 2002 to July 10, 2002
ISBN: 0-7695-1641-6
TABLE OF CONTENTS
Introduction

TTTC Information (PDF)

pp. 271
Session 1: Hardware Fault Tolerance

An Architecture for Self-Healing Digital Systems (Abstract)

B. Kiran Kumar , University of Arkansas
P. K. Lala , University of Arkansas
pp. 3

Coding Scheme for Low Energy Consumption Fault-Tolerant Bus (Abstract)

R. P. Kleihorst , Philips Research Laboratories
V. E. S. van Dijk , Philips Research Laboratories
C. Metra , University of Bologna
A. H. Nieuwland , Philips Research Laboratories
D. Rossi , University of Bologna
pp. 8

Survivable Discrete Circuits Design (Abstract)

A. Matrosova , Tomsk State University
V. Andreeva , Tomsk State University
Yu. Sedov , Tomsk State University
pp. 13
Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems

Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods (Abstract)

Petr Grillinger , University of West Bohemia
Pavel Herout , University of West Bohemia
Astrit Ademaj , Vienna University of Technology
Jan Hlavicka , Czech Technical University
pp. 21

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions (Abstract)

S. Chiusano , Politechnico di Torino
S. DiI Carlo , Politechnico di Torino
P. Prinetto , Politechnico di Torino
pp. 26

A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems (Abstract)

D. Sciuto , Politecnico di Milano
C. Bolchini , Politecnico di Milano
L. Pomante , Politecnico di Milano
F. Salice , Politecnico di Milano
pp. 32
Session 3: Self Checking Circuits

A New Self-Checking Code-Disjoint Carry-Skip Adder (Abstract)

V. Ocheretnij , University of Potsdam
E. S. Sogomonyan , University of Potsdam
M. Gössel , University of Potsdam
D. Marienfeld , University of Potsdam
pp. 39

Sequential Circuits Applicable for Detecting Different Types of Faults (Abstract)

I. Levin , Tel-Aviv University
M. Karpovsky , Boston University
S. Ostanin , Tel-Aviv University
V. Sinelnikov , Tel-Aviv University
pp. 44
Session 4: Concurrent Error Detection I

A High Speed Encoder for Recursive Systematic Convolutive Codes (Abstract)

F. Monteiro , LICM/CLOES, SUPELEC & University of Metz
B. Lepley , LICM/CLOES, SUPELEC & University of Metz
A. M?sir , LICM/CLOES, SUPELEC & University of Metz
A. Dandache , LICM/CLOES, SUPELEC & University of Metz
pp. 51

A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing (Abstract)

D. Nikolos , University of Patras
A. Arapoyanni , University of Athens
Y. Tsiatouhas , ISD S.A.
Th. Haniotakis , Southern Illinois University
pp. 56

Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Huy Nguyen , Georgia Institute of Technology
pp. 61
Session 5: Concurrent Error Detection II

On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check (Abstract)

M. Pflanz , IBM Deutschland Entwicklung GmbH
K. Walther , Brandenburg Technical University of Cottbus
C. Galke , Brandenburg Technical University of Cottbus
H. T. Vierhaus , Brandenburg Technical University of Cottbus
pp. 69

On-Line Monitor Design of Finite-State Machines (Abstract)

Feng Gao , University of Michigan
John P. Hayes , University of Michigan
pp. 74

A Statistical Sampler for a New On-line Analog Test Method (Abstract)

L. Carro , Universidade Federal do Rio Grande do Sul
A. A. Susin , Universidade Federal do Rio Grande do Sul
M. Negreiros , Universidade Federal do Rio Grande do Sul
pp. 79
Session 6: Analog and Mixed Signal Testing and Reliability

A ΣΔ A/D Converter Insensitive to SEU Effects (PDF)

Altamiro Suzim , Universidade Federal do Rio Grande do Sul
Alessandro Girardi , Universidade Federal do Rio Grande do Sul
Fernando Paixão Cortes , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. null

A BICS for CMOS Opamps by Monitoring the Supply Current Peak (Abstract)

J. Segura , Universitat Illes Balears
J. Font , Universitat Illes Balears
J. Ginard , Universitat Illes Balears
E. García , Universitat Illes Balears
E. Isern , Universitat Illes Balears
M. Roca , Universitat Illes Balears
pp. 94

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours (Abstract)

L. Balado , Universitat Polit?cnica de Catalunya
R. Rodríguez-Montañés , Universitat Polit?cnica de Catalunya
D. Muñoz , Universitat Polit?cnica de Catalunya
J. Figueras , Universitat Polit?cnica de Catalunya
pp. 99
Session 7: Fault Injection Techniques and Results

Analysis of SEU Effects in a Pipelined Processor (Abstract)

M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 112

Bit Flip Injection in Processor-Based Architectures: A Case Study (Abstract)

M. Ottavi , University of Rome "Tor Vergata"
S. Pontarelli , University of Rome "Tor Vergata"
R. Velazco , TIMA laboratory
F. Kaddour , TIMA laboratory
G. C. Cardarilli , University of Rome "Tor Vergata"
A. Leandri , University of Rome "Tor Vergata"
pp. 117
Session 8: BIST Techniques I

BIST-Based Delay-Fault Testing in FPGAs (Abstract)

Miron Abramovici , Agere Systems
Charles Stroud , University of North Carolina at Charlotte
pp. 131

Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing (Abstract)

N. Axelos , University of Huddersfield
J. Watson , University of Huddersfield
D. Taylor , University of Huddersfield
A. Platts , University of Huddersfield
pp. 135

A Low Power Pseudo-Random BIST Technique (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
Nadir Z. Basturkmen , University of Iowa
pp. 140
Session 9: BIST Techniques II

Stop & Go BIST (Abstract)

Bernd Becker , Albert-Ludwigs-University
Ilia Polian , Albert-Ludwigs-University
pp. 147

Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register (Abstract)

D. Bakalis , University of Patras and Computer Technology Institute
D. Nikolos , University of Patras and Computer Technology Institute
G. Dimitrakopoulos , University of Patras
pp. 152
Session 10: Testing Issues

Checkers for RF Matching Networks on an Automatic Test Board (Abstract)

Maria Grazia La Rosa , STMicroelectronics
Biagio Russo , STMicroelectronics
Giuseppe Di Gregorio , STMicroelectronics
pp. 170
Session 11: Posters

On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures (PDF)

H. T. Vierhaus , Brandenburg University of Technology Cottbus
M. Pflanz , IBM Deutschland Entwicklung GmbH
C. Galke , Brandenburg University of Technology Cottbus
pp. 178

Learning-Based On-Line Testing in Feedforward Neural Networks (Abstract)

Nobuyuki Matsui , Himeji Institute of Technology
Kazuharu Yamato , Hyogo University
Teijiro Isokawa , Himeji Institute of Technology
Naotake Kamiura , Himeji Institute of Technology
pp. 180

On-Line Detection of Short Circuits in Digital Devices and Systems (PDF)

Adam Kristof , Silesian University of Technology in Gliwice
pp. 183

Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach (PDF)

M. Rakotoar , TIMA Laboratory
C. Aktouf , LCIS-ESISAR
M. A. Naal , TIMA Laboratory
E. Simeu , TIMA Laboratory
pp. 184

Robust Data Compression for Analogue Test Outputs (PDF)

John Webster , Leeds Metropolitan University
Aleksandra Rankov , Leeds Metropolitan University
Gaynor E. Taylor , Leeds Metropolitan University
pp. 186

A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems (PDF)

R. D. Fagundes , Catholic University - PUCRS
F. Vargas , Catholic University - PUCRS
D. Barros Jr. , Catholic University - PUCRS
pp. 187

Radiation Effects Facility RADEF (PDF)

Ari Virtanen , University of Jyv?skyl?
pp. 188

Sequential n -Detection Criteria: Keep It Simple! (PDF)

Nicolai Mallig , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Ilia Polian , Albert-Ludwigs-University
Martin Keim , Mentor Graphics Corp.
pp. 189

An Off-Chip Sensor Circuit for On-Line Transient Current Testing (PDF)

B. Alorda , Université de les Illes Balears
A. Ivanov , University of British Columbia
J. Segura , Université de les Illes Balears
pp. 192

Analysis of the Equivalences and Dominances of Transient Faults at the RT Level (PDF)

Fulvio Corno , Polit?cnico di Torino
Matteo Sonza , Polit?cnico di Torino
Isabel González , Alcatel Espacio
Giovanni Squillero , Polit?cnico di Torino
Celia López , Universidad Carlos III de Madrid
Luis Berrojo , Alcatel Espacio
Luis Entrena , Universidad Carlos III de Madrid
pp. 193

Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller (PDF)

F. Lima , Federal University of Rio Grande do Sul
R. Reis , Federal University of Rio Grande do Sul
R. Velazco , TIMA Laboratory
L. Carro , Federal University of Rio Grande do Sul
pp. 194
Session 12: Memory BIST Analysis and Application

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques (Abstract)

A. Fudoli , STMicroelectronics
F. Corno , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
D. Appello , STMicroelectronics
V. Tancorre , STMicroelectronics
pp. 206

A Scan-Bist Environment for Testing Embedded Memories (Abstract)

F. Karimi , LTX Corporation
F. Lombardi , Northeastern University
pp. 211
Session 13: Memory ECC and Soft Errors

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories (Abstract)

C. Metra , University of Bologna
D. Rossi , University of Bologna
B. Riccò , University of Bologna
pp. 221

High Speed 15 ns 4 Mbits SRAM for Space Application (Abstract)

Olivier Husson , Atmel Corporation
Bernard Coloma , Atmel Corporation
Patrick Delaunay , Atmel Corporation
pp. 226
Session 14: High Reliability in Railway and Automotive Systems

Fault Tolerant Insertion and Verification: A Case Study (Abstract)

Diego De Costantini , Centro Ricerche FIAT
Alberto Manzone , Centro Ricerche FIAT
pp. 238

Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems (Abstract)

Cecilia Metra , University of Bologna
Diego Marino , Alstom Transport Spa
Luca Schiano , University of Bologna
pp. 243
Session 15: Embedded Memory Yield Enhancement

A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios (Abstract)

E. Rondey , Altis Semiconductor
Y. Tellier , Infineon Technologies
S. Borri , Infineon Technologies
pp. 251

A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories (Abstract)

Jen-Chieh Yeh , National Tsing Hua University
Rei-Fu Huang , National Tsing Hua University
Jin-Fu Li , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 262
Author Index

Author Index (PDF)

pp. 269
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