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On-Line Testing Workshop, IEEE International (2000)
Palma de Mallorca, Spain
July 3, 2000 to July 5, 2000
ISBN: 0-7695-0646-1
pp: 214
A. Benso , Politecnico di Torino
S. Chiusano , Politecnico di Torino
G. Di Natale , Politecnico di Torino
P. Prinetto , Politecnico di Torino
Monica Lobetti Bodoni , Siemens Information and Communication Networks S.p.A.
ABSTRACT
In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed On-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed, ranging from an external test to an On-line concurrent BIST.
INDEX TERMS
Memory Self-Repair, BISR, Memory BIST
CITATION

M. L. Bodoni, P. Prinetto, S. Chiusano, A. Benso and G. D. Natale, "A Family of Self-Repair SRAM Cores," On-Line Testing Workshop, IEEE International(IOLTW), Palma de Mallorca, Spain, 2000, pp. 214.
doi:10.1109/OLT.2000.856639
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