The Community for Technology Leaders
11th IEEE International On-Line Testing Symposium (2012)
Sitges, Spain Spain
June 27, 2012 to June 29, 2012
ISBN: 978-1-4673-2082-5
TABLE OF CONTENTS
Papers

Through-silicon-via built-in self-repair for aggressive 3D integration (Abstract)

Lorena Anghel , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
Vladimir Pasca , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
Michael Nicolaidis , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
pp. 91-96

RIIF - Reliability information interchange format (Abstract)

Adrian Evans , Cisco Systems Inc., USA
Enrico Costenaro , iRoC Technologies, USA
Dan Alexandrescu , iRoC Technologies, USA
Shi-Jie Wen , Cisco Systems Inc., USA
Michael Nicolaidis , TIMA Laboratory (Grenoble INP, UJF, CNRS), France
pp. 103-108

A fault attack robust TRNG (Abstract)

E. Bohl , Automotive Electronics Division, Robert Bosch GmbH, Germany
M. Ihle , Corporate Research Dept., Robert Bosch GmbH, Germany
pp. 114-117

Architectural vulnerability aware checkpoint placement in a multicore processor (Abstract)

Atieh Lotfi , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Arash Bayat , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Saeed Safari , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
pp. 118-120

Event-driven on-line co-simulation with fault diagnostic (Abstract)

Mikhail Baklashov , Intel Corp., 2200 Mission College Blvd., Santa Clara, CA USA
pp. 123-126

Functional level embedded self testing for Walsh transform based adaptive hardware (Abstract)

Ariel Burg , School of Engineering, Bar-Ilan University, Israel
Osnat Keren , School of Engineering, Bar-Ilan University, Israel
pp. 134-135

Neutron-induced soft error rate estimation for SRAM using PHITS (Abstract)

Shusuke Yoshimoto , Kobe University, Japan
Takuro Amashita , Kobe University, Japan
Masayoshi Yoshimura , Kyushu University, Japan
Yusuke Matsunaga , Kyushu University, Japan
Hiroto Yasuura , JST CREST Japan
Shintaro Izumi , Kobe University, Japan
Hiroshi Kawaguchi , Kobe University, Japan
Masahiko Yoshimoto , JST CREST Japan
pp. 138-141

Reliable and secure memories based on algebraic manipulation correction codes (Abstract)

Zhen Wang , Reliable Computing Laboratory, Boston University, USA
Mark Karpovsky , Reliable Computing Laboratory, Boston University, USA
pp. 146-149

Analysis of FinFET technology on memories (Abstract)

E. Amat , Universitat Politècnica de Catalunya, UPC, Barcelona, Spain
A. Asenov , University of Glasgow, Scotland
R. Canal , Universitat Politècnica de Catalunya, UPC, Barcelona, Spain
B. Cheng , University of Glasgow, Scotland
J-Ll. Cruz , Universitat Politècnica de Catalunya, UPC, Barcelona, Spain
Z. Jaksic , Universitat Politècnica de Catalunya, UPC, Barcelona, Spain
M. Miranda , Imec, Leuven, Belgium
A. Rubio , Universitat Politècnica de Catalunya, UPC, Barcelona, Spain
P. Zuber , Imec, Leuven, Belgium
pp. 169

Towards optimized functional evaluation of SEE-induced failures in complex designs (Abstract)

Dan Alexandrescu , iRoC Technologies, Grenoble, France
Enrico Costenaro , iRoC Technologies, Grenoble, France
pp. 182-187

[Front matter] (Abstract)

pp. i-xx

Soft-errors resilient logic optimization for low power (Abstract)

Sujan Pandey , NXP Semiconductors/Research - Eindhoven, The Netherlands
Klaas Brink , NXP Semiconductors/Research - Eindhoven, The Netherlands
pp. 19-24

Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster (Abstract)

Arwa Ben Dhia , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS France
Lirida Naviner , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS France
Philippe Matherat , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS France
pp. 31-36

Transparent structural online test for reconfigurable systems (Abstract)

Mohamed S. Abdelfattah , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Lars Bauer , Embedded Systems, Karlsruhe Institute of Technology, Germany
Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael A. Kochte , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Hongyan Zhang , Embedded Systems, Karlsruhe Institute of Technology, Germany
Jorg Henkel , Embedded Systems, Karlsruhe Institute of Technology, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
pp. 37-42

Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons (Abstract)

Eishi Ibe , Yokohama Research Laboratory, Hitachi, Ltd., 292 Yoshida, Totsuka, Kanagawa, 244-0817, Japan
Tadanobu Toba , Yokohama Research Laboratory, Hitachi, Ltd., 292 Yoshida, Totsuka, Kanagawa, 244-0817, Japan
Ken-ichi Shimbo , Yokohama Research Laboratory, Hitachi, Ltd., 292 Yoshida, Totsuka, Kanagawa, 244-0817, Japan
Hitoshi Taniguchi , Yokohama Research Laboratory, Hitachi, Ltd., 292 Yoshida, Totsuka, Kanagawa, 244-0817, Japan
pp. 49-54

Neutron radiation test of graphic processing units (Abstract)

P. Rech , UFRGS, Umversidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
C. Aguiar , UFRGS, Umversidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
R. Ferreira , UFRGS, Umversidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
C. Frost , ISIS, Rutherford Appleton Laboratories, Didcot, UK
L. Carro , UFRGS, Umversidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 55-60

Low Power embedded DRAM caches using BCH code partitioning (Abstract)

Pedro Reviriego , Universidad Antonio de Nebrija, C/Pirineos, 55, E-28040, Madrid, Spain
Alfonso Sanchez-Macian , Universidad Antonio de Nebrija, C/Pirineos, 55, E-28040, Madrid, Spain
Juan Antonio Maestro , Universidad Antonio de Nebrija, C/Pirineos, 55, E-28040, Madrid, Spain
pp. 79-83
Papers

Fault coverage of a timing and control flow checker for hard real-time systems (Abstract)

Julian Wolf , University of Augsburg, Germany
Bernhard Fechner , University of Augsburg, Germany
Theo Ungerer , University of Augsburg, Germany
pp. 127-129

Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design (Abstract)

Wenhui Yang , Department of Communication Engineering, Xiamen University, China
pp. 130-133

Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports (Abstract)

Francisco R. Fernandes , Department of Electrical and Computer Engineering, FEUP, Porto, Portugal
Ricardo J. S. Machado , Department of Electrical and Computer Engineering, FEUP, Porto, Portugal
Jose M. Ferreira , Department of Electrical and Computer Engineering, FEUP, Porto, Portugal
Manuel G. Gericota , Department of Electrical Engineering, ISEP, Porto, Portugal
pp. 136-137

Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis (Abstract)

Sabyasachi Deyati , School of ECE, Georgia Institute of Technology, Atlanta, 30332, USA
Aritra Banerjee , School of ECE, Georgia Institute of Technology, Atlanta, 30332, USA
Abhijit Chatterjee , School of ECE, Georgia Institute of Technology, Atlanta, 30332, USA
pp. 142-145

Algorithmic techniques for robust applications (Abstract)

Rakesh Kumar , University of Illinois, Urbana-Champaign, USA
pp. 168

An efficient probability framework for error propagation and correlation estimation (Abstract)

Liang Chen , Karlsruhe Institute of Technology, Germany
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Germany
pp. 170-175

Logic masking for SET Mitigation Using Approximate Logic Circuits (Abstract)

A. Sanchez-Clemente , Electronic Technology Department, Universidad Carlos III de Madrid, Spain
L. Entrena , Electronic Technology Department, Universidad Carlos III de Madrid, Spain
M. Garcia-Valderas , Electronic Technology Department, Universidad Carlos III de Madrid, Spain
C. Lopez-Ongil , Electronic Technology Department, Universidad Carlos III de Madrid, Spain
pp. 176-181

SEU sensitivity of robust communication protocols (Abstract)

C. Lopez-Ongil , Electronic Technology Department, University Carlos III of Madrid, Leganes, Spain
M. Portela-Garcia , Electronic Technology Department, University Carlos III of Madrid, Leganes, Spain
M. Garcia-Valderas , Electronic Technology Department, University Carlos III of Madrid, Leganes, Spain
A. Vaskova , Electronic Technology Department, University Carlos III of Madrid, Leganes, Spain
L. Entrena , Electronic Technology Department, University Carlos III of Madrid, Leganes, Spain
J. Rivas-Abalo , INTA (National Institute for Aerospace Technique), Madrid, Spain
A. Martin-Ortega , INTA (National Institute for Aerospace Technique), Madrid, Spain
J. Martinez-Oter , INTA (National Institute for Aerospace Technique), Madrid, Spain
S. Rodriguez-Bustabad , INTA (National Institute for Aerospace Technique), Madrid, Spain
I. Arruego , INTA (National Institute for Aerospace Technique), Madrid, Spain
pp. 188-193

SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems (Abstract)

Yang Lin , Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
Mark Zwolinski , Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
pp. 7-12

SEU tolerant robust memory cell design (Abstract)

Md Shayan , Indian Institute of Science, Bangalore, India
Virendra Singh , Indian Institute of Technology, Bombay, India
Adit D Singh , Auburn University, USA
Masahiro Fujita , University of Tokyo, Japan
pp. 13-18

SEU-X: A SEu un-excitability prover for SRAM-FPGAs (Abstract)

Cinzia Bernardeschi , Department of Information Engineering, University of Pisa, Italy
Luca Cassano , Department of Information Engineering, University of Pisa, Italy
Andrea Domenici , Department of Information Engineering, University of Pisa, Italy
pp. 25-30

A real-case application of a synergetic design-flow-oriented SER analysis (Abstract)

Miguel Vilchis , LSI Corporation, Milpitas, CA, USA
Ramnath Venkatraman , LSI Corporation, Milpitas, CA, USA
Enrico Costenaro , iRoC Technologies, Grenoble, France
Dan Alexandrescu , iRoC Technologies, Grenoble, France
pp. 43-48

The influence of clock-gating on NBTI-induced delay degradation (Abstract)

J. Pachito , Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal
C. V. Martins , Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal
J. Semiao , Univ. of Algarve / INESC-ID Lisbon, Faro, Portugal
M. Santos , INESC-ID Lisbon / IST-UTL, Portugal
I. C. Teixeira , INESC-ID Lisbon / IST-UTL, Portugal
J. P. Teixeira , INESC-ID Lisbon / IST-UTL, Portugal
pp. 61-66

Relation between HCI-induced performance degradation and applications in a RISC processor (Abstract)

C. Bertolini , CEA, LIST, PC127, F-91191 Gif-sur-Yvette, France
O. Heron , CEA, LIST, PC127, F-91191 Gif-sur-Yvette, France
N. Ventroux , CEA, LIST, PC127, F-91191 Gif-sur-Yvette, France
F. Marc , Université Bordeaux I, 351 cours de la Libération, 33405 TALENCE cedex, France
pp. 67-72

Do more camera pixels result in a better picture? (Abstract)

Glenn H. Chapman , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Israel Koren , Dept. of Elec. and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
Zahava Koren , Dept. of Elec. and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
pp. 73-78

Test access mechanism for chips with spare identical cores (Abstract)

Ozgur Sinanoglu , Computer Engineering Department, New York University - Abu Dhabi, United Arab Emirates
pp. 97-102

On line monitoring of RF power amplifiers with embedded temperature sensors (Abstract)

Josep Altet , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
Diego Mateo , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
Didac Gomez , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 109-113

Cross-level protection of circuits against faults and malicious attacks (Abstract)

Victor Tomashevich , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Sudarshan Srinivasan , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Fabian Foerg , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Ilia Polian , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
pp. 150-155

Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices (Abstract)

Yaara Neumeier , School of Engineering, Bar-Ilan University, Israel
Osnat Keren , School of Engineering, Bar-Ilan University, Israel
pp. 156-161

Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors (Abstract)

Ameya Chaudhari , Computer Engineering Research Center, University of Texas at Austin -78712, USA
Jacob Abraham , Computer Engineering Research Center, University of Texas at Austin -78712, USA
pp. 162-167

On the functional test of L2 caches (Abstract)

M. Riga , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
E. Sanchez , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
pp. 84-90
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