The Community for Technology Leaders
11th IEEE International On-Line Testing Symposium (2011)
Athens
July 13, 2011 to July 15, 2011
ISBN: 978-1-4577-1053-7
TABLE OF CONTENTS
Papers

Front matter (Abstract)

pp. i-xi

[Front matter] (PDF)

pp. i-xi
Papers

Investigation of multi cell upset in sequential logic and validity of redundancy technique (Abstract)

K. Takahisa , Osaka Univ., Suita, Japan
H. Matsuyama , Fujitsu Semicond. Ltd., Tokyo, Japan
M. Fukuda , Osaka Univ., Suita, Japan
K. Hatanaka , Osaka Univ., Suita, Japan
T. Kato , Fujitsu Semicond. Ltd., Tokyo, Japan
T. Uemura , Fujitsu Semicond. Ltd., Tokyo, Japan
pp. 7-12

High-level synthesis for multi-cycle transient fault tolerant datapaths (Abstract)

Y. Yoshikawa , Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
H. Ichihara , Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
T. Inoue , Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
H. Henmi , Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
pp. 13-18

An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems (Abstract)

F. Vargas , Electr. Eng. Dept., Catholic Univ. - PUCRS, Porto Alegre, Brazil
L. Bolzani , Electr. Eng. Dept., Catholic Univ. - PUCRS, Porto Alegre, Brazil
D. Silva , Electr. Eng. Dept., Catholic Univ. - PUCRS, Porto Alegre, Brazil
pp. 19-24

RVC-based time-predictable faulty caches for safety-critical systems (Abstract)

J. Abella , Barcelona Supercomput. Center, Barcelona, Spain
E. Quiñones , Barcelona Supercomput. Center, Barcelona, Spain
Y. Sazeides , Univ. of Cyprus, Nicosia, Cyprus
F. J. Cazorla , Barcelona Supercomput. Center, Barcelona, Spain
M. Valero , Barcelona Supercomput. Center, Barcelona, Spain
pp. 25-30

Towards functional-safe timing-dependable real-time architectures (Abstract)

R. Mariani , YOGITECH SpA, Pisa, Italy
M. Paolieri , Barcelona Supercomput. Center, Barcelona, Spain
pp. 31-36

Matrix control-flow algorithm-based fault tolerance (Abstract)

L. Carro , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
R. R. Ferreira , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A. F. Moreira , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 37-42

Selective fault tolerance for finite state machines (Abstract)

R. Kraemer , IHP, Frankfurt (Oder), Germany
M. Gossel , Comput. Sci. Inst., Potsdam Univ., Potsdam, Germany
M. Augustin , Comput. Sci. Inst., BTU Cottbus, Cottbus, Germany
pp. 43-48

A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories (Abstract)

D. Alexandrescu , iRoC Technol., Grenoble, France
M. Violante , Dipt. di Autom. e Inf. Torino, Politec. di Torino, Torino, Italy
E. Costenaro , iRoC Technol., Grenoble, France
pp. 49-54

Variability-aware task mapping strategies for many-cores processor chips (Abstract)

F. Chaix , Tech. of Inf. & Microelectron. for Integrated Syst. Archit., Grenoble Univ., Grenoble, France
G. Bizot , Tech. of Inf. & Microelectron. for Integrated Syst. Archit., Grenoble Univ., Grenoble, France
Nacer-Eddine Zergainoh , Tech. of Inf. & Microelectron. for Integrated Syst. Archit., Grenoble Univ., Grenoble, France
M. Nicolaidis , Tech. of Inf. & Microelectron. for Integrated Syst. Archit., Grenoble Univ., Grenoble, France
pp. 55-60

On graceful degradation of microprocessors in presence of faults via resource banking (Abstract)

S. Kundu , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
R. Rodrigues , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
pp. 61-66

On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units (Abstract)

R. Rodrigues , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
S. Kundu , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
pp. 67-72

A multi-objective optimization for memory BIST sharing using a genetic algorithm (Abstract)

A. Wenzel , STMicroelectronics, Crolles, France
L. Zaourar , SOC Dept., LIP6 Lab., Paris, France
Y. Kieffer , G-SCOP Lab., Grenoble, France
pp. 73-78

Memory BIST with address programmability (Abstract)

A. Fradi , Electron. & Microelectron. Lab., Monastir, Tunisia
L. Anghel , TIMA Lab., UJF, Grenoble, France
M. Nicolaidis , TIMA Lab., UJF, Grenoble, France
pp. 79-85

A reliable fault classifier for dependable systems on SRAM-based FPGAs (Abstract)

L. Fossati , Eur. Space Agency, Noordwijk, Netherlands
C. Sandionigi , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
D. M. Codinachs , Eur. Space Agency, Noordwijk, Netherlands
C. Bolchini , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
pp. 92-97

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities (Abstract)

J. M. Daveau , Central CAD & Design Solutions (CCDS), STMicrolectronics, Crolles, France
P. Roche , Central CAD & Design Solutions (CCDS), STMicrolectronics, Crolles, France
J. T. Flaquer , Central CAD & Design Solutions (CCDS), STMicrolectronics, Crolles, France
L. Naviner , COMELEC Dept., Telecom Paristech, Paris, France
pp. 98-103

Estimation of component criticality in early design steps (Abstract)

B. Becker , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
M. Sauer , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
I. Polian , Univ. of Passau, Passau, Germany
A. Czutro , Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
pp. 104-110

New reliability mechanisms in memory design for sub-22nm technologies (Abstract)

J. Figueras , Univ. Politec. de Catalunya, Barcelona, Spain
X. Wang , Univ. of Glasgow, Glasgow, UK
T. Ramirez , Intel, Barcelona, Spain
A. Gonzalez , Intel, Barcelona, Spain
N. Aymerich , Univ. Politec. de Catalunya, Barcelona, Spain
A. Brown , Univ. of Glasgow, Glasgow, UK
R. Canal , Univ. Politec. de Catalunya, Barcelona, Spain
P. Pouyan , Univ. Politec. de Catalunya, Barcelona, Spain
I. Vatajelu , Univ. Politec. de Catalunya, Barcelona, Spain
B. Cheng , Univ. of Glasgow, Glasgow, UK
P. Zuber , Imec, Leuven, Belgium
M. Miranda , Imec, Leuven, Belgium
X. Vera , Intel, Barcelona, Spain
A. Asenov , Univ. of Glasgow, Glasgow, UK
S. Markov , Univ. of Glasgow, Glasgow, UK
A. Rubio , Univ. Politec. de Catalunya, Barcelona, Spain
E. Herrero , Intel, Barcelona, Spain
pp. 111-114

A BIST scheme for testing and repair of multi-mode power switches (Abstract)

X. Kavousianos , Dept. Comput. Sci., Univ. of Ioannina, Ioannina, Greece
K. Chakrabarty , Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
Y. Tsiatouhas , Dept. Comput. Sci., Univ. of Ioannina, Ioannina, Greece
Zhaobo Zhang , Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 115-120

Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems (Abstract)

R. Alhakim , TIMA Lab., Grenoble Univ., Grenoble, France
K. Raoof , GIPSA-Lab., Grenoble Univ., St. Martin d'Heres, France
E. Simeu , TIMA Lab., Grenoble Univ., Grenoble, France
pp. 121-126

Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control (Abstract)

S. Sen , Dept. of Electical & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Dept. of Electical & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
J. Natarajan , Dept. of Electical & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 127-132

The cost of cryptography: Is low budget possible? (Abstract)

I. Verbauwhede , ESAT/COSIC, K.U. Leuven, Leuven, Belgium
pp. 133

Countermeasures against fault attacks: The good, the bad, and the ugly (Abstract)

P. Maistri , TIMA Lab., UJF, Grenoble, France
pp. 134-137

Rise of the hardware Trojans (Abstract)

B. Sunar , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
pp. 138

A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS (Abstract)

A. Rajendran , Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Case Western Reserve Univ., Cleveland, OH, USA
Y. Shiyanovskii , Case Western Reserve Univ., Cleveland, OH, USA
pp. 139-144

Noise margin, critical charge and power-delay tradeoffs for SRAM design (Abstract)

Y. Shiyanovskii , Case Western Reserve Univ., Cleveland, OH, USA
A. Rajendran , Case Western Reserve Univ., Cleveland, OH, USA
F. Wolff , Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Case Western Reserve Univ., Cleveland, OH, USA
pp. 145-150

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure (Abstract)

S. Yoshimoto , Kobe Univ., Kobe, Japan
H. Kawaguchi , Kobe Univ., Kobe, Japan
M. Yoshimoto , CREST, JST, Saitama, Japan
T. Takata , Kyushu Univ., Fukuoka, Japan
D. Kozuwa , Kyushu Univ., Fukuoka, Japan
T. Amashita , Kobe Univ., Kobe, Japan
M. Yoshimura , Kyushu Univ., Fukuoka, Japan
H. Yasuura , CREST, JST, Saitama, Japan
Y. Matsunaga , Kyushu Univ., Fukuoka, Japan
pp. 151-156

Error correction encoding for multi-threshold capture mechanism (Abstract)

S. Tragoudas , Dept. of Electr. & Comput. Eng., Southern Illinois Univ. at Carbondale, Carbondale, IL, USA
K. Karmarkar , Dept. of Electr. & Comput. Eng., Southern Illinois Univ. at Carbondale, Carbondale, IL, USA
pp. 157-162

Reduced overhead soft error mitigation using error control coding techniques (Abstract)

V. Singh , Comput. Design & Test Lab., Indian Inst. of Sci., Bangalore, India
R. Parekhji , Texas Instrum. (India) Pvt. Ltd., Bangalore, India
V. Prasanth , Comput. Design & Test Lab., Indian Inst. of Sci., Bangalore, India
pp. 163-168

Soft error correction in embedded storage elements (Abstract)

Hans-Joachim Wunderlich , Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
M. E. Imhof , Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
pp. 169-174

A verification strategy for fault-detection and fault-tolerance circuits (Abstract)

S. Lorenzini , Yogitech SpA, Pisa, Italy
R. Mariani , Yogitech SpA, Pisa, Italy
G. Boschi , Yogitech SpA, Pisa, Italy
pp. 177-178

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness (Abstract)

A. Vaskova , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
C. Lopez-Ongil , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
A. Jimenez-Horas , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
L. Entrena , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
E. S. Millan , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
pp. 179-181

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors (Abstract)

W. Burgard , Albert-Ludwigs-Univ., Freiburg, Germany
M. Sauer , Albert-Ludwigs-Univ., Freiburg, Germany
A. Spilla , Albert-Ludwigs-Univ., Freiburg, Germany
M. Lewis , Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker , Albert-Ludwigs-Univ., Freiburg, Germany
I. Polian , Univ. of Passau, Passau, Germany
V. Tomashevich , Univ. of Passau, Passau, Germany
J. Muller , Albert-Ludwigs-Univ., Freiburg, Germany
pp. 182-185

An on-line memory state validation using shadow memory cloning (Abstract)

M. Baklashov , Intel Corp., Santa Clara, CA, USA
pp. 186-189

Control-flow error recovery using commodity multi-core architecture features (Abstract)

H. R. Zarandi , Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran
N. Khoshavi , Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran
M. Maghsoudloo , Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran
pp. 190-191

Detection of Trojan HW by using hidden information on the system (Abstract)

O. Keren , Sch. of Eng., Bar Ilan Univ., Ramat Gan, Israel
I. Levin , Sch. of Educ., Tel Aviv Univ., Tel Aviv, Israel
V. Sinelnikov , Sch. of Eng., Bar Ilan Univ., Ramat Gan, Israel
pp. 192-193

Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire (Abstract)

H. R. Zarandi , Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran
R. Salamat , Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran
pp. 196-197

Generalized parity-check matrices for SEC-DED codes with fixed parity (Abstract)

S. Evain , Embedded Syst. Reliability Lab., CEA, Gif-sur-Yvette, France
V. Gherman , Embedded Syst. Reliability Lab., CEA, Gif-sur-Yvette, France
N. Seymour , Embedded Syst. Reliability Lab., CEA, Gif-sur-Yvette, France
Y. Bonhomme , Embedded Syst. Reliability Lab., CEA, Gif-sur-Yvette, France
pp. 198-201

ICT: Interface software for the characterization and test of mixed-signal power cores (Abstract)

T. H. Moita , Dept. of Electr. & Comput. Eng., UTL, Lisbon, Portugal
J. O. M. Esteves , Dept. of Electr. & Comput. Eng., UTL, Lisbon, Portugal
Marcelino B. dos Santos , Dept. of Electr. & Comput. Eng., UTL, Lisbon, Portugal
C. B. Almeida , Dept. of Electr. & Comput. Eng., UTL, Lisbon, Portugal
pp. 202-205

Loopback output router for reliable Network on Chip (Abstract)

A. Dandache , Lab. Interfaces, Sensors & Microelectron., Univ. of Paul Verlaine, Metz, France
C. Killian , Lab. Interfaces, Sensors & Microelectron., Univ. of Paul Verlaine, Metz, France
C. Tanougast , Lab. Interfaces, Sensors & Microelectron., Univ. of Paul Verlaine, Metz, France
F. Monteiro , Lab. Interfaces, Sensors & Microelectron., Univ. of Paul Verlaine, Metz, France
pp. 206-207

Multi-level secure JTAG architecture (Abstract)

L. Pierce , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 208-209

Self-checking test circuits for latches and flip-flops (Abstract)

A. Ivanov , Univ. of British Columbia, Vancouver, BC, Canada
Yuyang Sun , Univ. of British Columbia, Vancouver, BC, Canada
A. I. Reis , Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
R. P. Ribas , Univ. of British Columbia, Vancouver, BC, Canada
pp. 210-213

Software-based control flow error detection and correction using branch triplication (Abstract)

M. Fazeli , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
S. G. Miremadi , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
N. F. Ghalaty , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
H. I. Rad , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
pp. 214-217

Variations of fault manifestation during Burn-In -- A case study on industrial SRAM test results (Abstract)

K. Oberlander , Infineon Technol. AG, Neubiberg, Germany
A. Eder , Dept. of Electr. Eng., Univ. of Appl. Sci. Augsburg, Augsburg, Germany
M. Linder , Dept. of Electr. Eng., Univ. of Appl. Sci. Augsburg, Augsburg, Germany
M. Huch , Infineon Technol. AG, Neubiberg, Germany
pp. 218-221

A side channel attack countermeasure using system-on-chip power profile scrambling (Abstract)

J. Grinschgl , Inst. for Tech. Inf., Graz Univ. of Technol., Graz, Austria
R. Weiss , Inst. for Tech. Inf., Graz Univ. of Technol., Graz, Austria
A. Krieg , Inst. for Tech. Inf., Graz Univ. of Technol., Graz, Austria
J. Haid , Design Center Graz, Infineon Technol. Austria AG, Graz, Austria
C. Steger , Inst. for Tech. Inf., Graz Univ. of Technol., Graz, Austria
pp. 222-227

AKARI-X: A pseudorandom number generator for secure lightweight systems (Abstract)

Pedro Peris Lopez , Inf. & Commun. Theor. Group, Delft Univ. of Technol., Delft, Netherlands
Enrique San Millan , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
Luis Entrena , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
Honorio Martin , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
Julio Cesar Hernandez Castro , Sch. of Comput., Univ. of Portsmouth, Portsmouth, UK
pp. 228-233

Algebraic manipulation detection codes and their applications for design of secure cryptographic devices (Abstract)

Zhen Wang , Reliable Comput. Lab., Boston Univ., Boston, MA, USA
M. Karpovsky , Reliable Comput. Lab., Boston Univ., Boston, MA, USA
pp. 234-239

Towards improved survivability in safety-critical systems (Abstract)

E. Quinones , Barcelona Supercomput. Center (BSC), Barcelona, Spain
F. J. Cazorla , Barcelona Supercomput. Center (BSC), Barcelona, Spain
Dimitris Gizopoulos , Dept. of Inf. & Telecommun., Univ. of Athens, Athens, Greece
J. Abella , Barcelona Supercomput. Center (BSC), Barcelona, Spain
pp. 240-245

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits (Abstract)

Y. Matsunaga , Dept. of Adv. Inf. Technol., Kyushu Univ., Fukuoka, Japan
T. Takata , Dept. of Adv. Inf. Technol., Kyushu Univ., Fukuoka, Japan
pp. 246-251

An analytical model for the calculation of the Expected Miss Ratio in faulty caches (Abstract)

J. L. Aragon , Dept. of Comput. Eng., Univ. of Murcia, Murcia, Spain
D. Sanchez , Dept. of Comput. Eng., Univ. of Murcia, Murcia, Spain
J. M. Garcia , Dept. of Comput. Eng., Univ. of Murcia, Murcia, Spain
Y. Sazeides , Dept. of Comput. Sci., Univ. of Cyprus, Nicosia, Cyprus
pp. 252-257

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution (Abstract)

M. Garcia-Valderas , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
L. Entrena , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
A. Vaskova , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
M. Portela-Garcia , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
C. Lopez-Ongil , Electron. Technol. Dept., Carlos III Univ. of Madrid, Leganes, Spain
pp. 258-263

Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies (Abstract)

N. Madalin , Dept. of Syst. Eng., Tech. Univ. of Cluj-Napoca, Cluj-Napoca, Romania
L. Miclea , Dept. of Syst. Eng., Tech. Univ. of Cluj-Napoca, Cluj-Napoca, Romania
J. Figueras , Dept. of Electron. Eng., Univ. Politec. de Catalunya, Barcelona, Spain
pp. 264-269

An effective methodology for on-line testing of embedded microprocessors (Abstract)

M. S. Reorda , Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
L. Ciganda , Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
P. Bernardi , Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
E. Sanchez , Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
pp. 270-275

Fail-safety in core-based system design (Abstract)

R. Baranowski , Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
H. Wunderlich , Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
pp. 276-281
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