11th IEEE International On-Line Testing Symposium (2009)
June 24, 2009 to June 26, 2009
Marc Hunger , Institute of Electrical Engineering and Information Technology, University of Paderborn, Germany
Sybille Hellebrand , Institute of Electrical Engineering and Information Technology, University of Paderborn, Germany
Alejandro Czutro , Institute of Computer Science, University of Freiburg, Germany
Ilia Polian , Institute of Computer Science, University of Freiburg, Germany
Bernd Becker , Institute of Computer Science, University of Freiburg, Germany
Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considered, but also its robustness properties have to be analyzed. In this work we propose a method to verify the strong fault-secureness by use of constrained SAT-based ATPG. Strongly fault-secure circuits can be seen as the widest class of circuits achieving the totally self-checking (TSC) goal, which requires that every fault be detected the first time it manifests itself as an error at the outputs. As the strongly fault-secure property guarantees to achieve the TSC goal even in the case of fault accumulation, the effects of all possible fault sequences have to be taken into consideration to verify this property. To speed up the complex analysis of multiple faults we develop rules to derive detectability or redundancy information for multiple faults from the respective information for single faults. For the case of not strongly fault-secure circuits our method provides measures to grade the “extent” of strong fault-secureness given by the implementation.
A. Czutro, B. Becker, M. Hunger, S. Hellebrand and I. Polian, "ATPG-based grading of strong fault-secureness," 11th IEEE International On-Line Testing Symposium(IOLTS), Sesimbra-Lisbon, Portugal, 2009, pp. 269-274.