11th IEEE International On-Line Testing Symposium (2009)
June 24, 2009 to June 26, 2009
S. Baranov , Bar Ilan University/School of Engineering, Ramat Gan, Israel
M. Karpovsky , Boston University/Department of Electrical, Computer and System Engineering, USA
I. Levin , Tel Aviv University/School of Education, Israel
O. Keren , Bar Ilan University/School of Engineering, Ramat Gan, Israel
The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.
S. Baranov, M. Karpovsky, I. Levin, O. Keren, "Designing fault tolerant FSM by nano-PLA", 11th IEEE International On-Line Testing Symposium, vol. 00, no. , pp. 229-234, 2009, doi:10.1109/IOLTS.2009.5196021