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11th IEEE International On-Line Testing Symposium (2009)
Sesimbra-Lisbon, Portugal
June 24, 2009 to June 26, 2009
ISBN: 978-1-4244-4596-7
pp: 185-186
Fabian Vargas , Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Claudia A. Rocha , Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Bernardo Pianta , Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Marta Portela Garcia , Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Celia Lopez Ongil , Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Mario Garcia Valderas , Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Luis Entrena , Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
ABSTRACT
We propose an approach<sup>1</sup> to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.
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CITATION

M. G. Valderas et al., "Briefing power/reliability optimization in embedded software design," 11th IEEE International On-Line Testing Symposium(IOLTS), Sesimbra-Lisbon, Portugal, 2009, pp. 185-186.
doi:10.1109/IOLTS.2009.5196007
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