Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
11th IEEE International On-Line Testing Symposium (2009)
June 24, 2009 to June 26, 2009
Abhijit Chatterjee , Georgia Tech., USA
Jacob Abraham , University of Texas at Austin, USA
Adit Singh , Auburn University, USA
Elie Maricau , KU Leuven, Belgium
Rakesh Kumar , University of Illinois at Urbana-Champaign, USA
Christos Papachristou , Case Western Reserve University, USA
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?
Abhijit Chatterjee, Jacob Abraham, Adit Singh, Elie Maricau, Rakesh Kumar, Christos Papachristou, "Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?", 11th IEEE International On-Line Testing Symposium, vol. 00, no. , pp. 129, 2009, doi:10.1109/IOLTS.2009.5195994