11th IEEE International On-Line Testing Symposium (2009)
June 24, 2009 to June 26, 2009
Yuriy Shiyanovskii , Case Western Reserve University, Cleveland, Ohio 44106, USA
Frank Wolff , Case Western Reserve University, Cleveland, Ohio 44106, USA
Chris Papachristou , Case Western Reserve University, Cleveland, Ohio 44106, USA
A new SRAM cell model, SRAMT, is presented providing a scalable solution to soft error for various energy levels of protection with minimal power consumption and write time penalties. Our model is based on a classic 6 transistor inner core SRAM cell and an outer core consisting of enhanced tri-state inverters. The outer core will absorb a particle strike at a sensitive node of the SRAM cell without a major impact on write time performance or area overhead. The model provides an on-demand protection due to the fact that the outer core can be shut off during non-essential operating mode. The on-demand aspect of the design provides a much more favorable power consumption overhead compared to the existing hardening technique. The gains in power consumption overhead reduction increase as we scale down the process technology from 90nm to 32nm. We simulated extensively our model and provided results for various energy levels of soft error protection. We also compared our method to the standard hardening technique in terms of layout area, performance and power consumption overhead for for 90nm, 65nm, 45nm and 32nm process technologies.
Y. Shiyanovskii, F. Wolff and C. Papachristou, "SRAM cell design using tri-state devices for SEU protection," 11th IEEE International On-Line Testing Symposium(IOLTS), Sesimbra-Lisbon, Portugal, 2009, pp. 114-119.