11th IEEE International On-Line Testing Symposium (2009)
June 24, 2009 to June 26, 2009
C. Guardiani , Elite-DC S.r.l., Italy
A. Shibkov , Elite-DC S.r.l., Italy
A. Brambilla , Politecnico di Milano, Italy
G. Storti Gajani , Politecnico di Milano, Italy
D. Appello , ST Microelectronics S.r.l., Italy
F. Piazza , ST Microelectronics S.r.l., Italy
P. Bernardi , Politecnico di Torino, Italy
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V<inf>TH</inf> degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.
D. Appello et al., "An I-IP based approach for the monitoring of NBTI effects in SoCs," 11th IEEE International On-Line Testing Symposium(IOLTS), Sesimbra-Lisbon, Portugal, 2009, pp. 15-20.