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11th IEEE International On-Line Testing Symposium (2009)
Sesimbra-Lisbon, Portugal
June 24, 2009 to June 26, 2009
ISBN: 978-1-4244-4596-7
pp: 15-20
D. Appello , ST Microelectronics S.r.l., Italy
A. Brambilla , Politecnico di Milano, Italy
G. Storti Gajani , Politecnico di Milano, Italy
F. Piazza , ST Microelectronics S.r.l., Italy
P. Bernardi , Politecnico di Torino, Italy
C. Guardiani , Elite-DC S.r.l., Italy
A. Shibkov , Elite-DC S.r.l., Italy
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V<inf>TH</inf> degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.
D. Appello, A. Brambilla, G. Storti Gajani, F. Piazza, P. Bernardi, C. Guardiani, A. Shibkov, "An I-IP based approach for the monitoring of NBTI effects in SoCs", 11th IEEE International On-Line Testing Symposium, vol. 00, no. , pp. 15-20, 2009, doi:10.1109/IOLTS.2009.5195977
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