The Community for Technology Leaders
11th IEEE International On-Line Testing Symposium (2007)
Heraklion, Crete, Greece
July 8, 2007 to July 11, 2007
ISBN: 0-7695-2918-6
TABLE OF CONTENTS
Introduction

Program Committee (PDF)

pp. xiii
Test Technology Educational Program (TTEP) 2007 Full-Day Tutorial
Keynote Talk
Invited Talk

Accelerating Yield Ramp through Real-Time Testing (PDF)

Sanjiv Taneja , Vice President and General Manager of Test Technology Cadence
pp. 11
Session 1: Reliability Issues in Nanometer Technologies

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs (Abstract)

Osman Unsal , Intel Barcelona Research Center
Antonio Gonz?lez , Intel Barcelona Research Center
Xavier Vera , Intel Barcelona Research Center
Oguz Ergin , Intel Barcelona Research Center
Jaume Abella , Intel Barcelona Research Center
pp. 15-22

Design for Resilience to Soft Errors and Variations (Abstract)

Norbert Seifert , Intel Corporation
Kee Sup Kim , Intel Corporation
Davia Lu , Intel Corporation
T.M. Mak , Intel Corporation
Ming Zhang , Intel Corporation
Jim Tschanz , Intel Corporation
pp. 23-28

Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield (Abstract)

Rajat Subhra. Chakraborty , Case Western Reserve University, USA
Swarup Bhunia , Case Western Reserve University, USA
Somnath Paul , Case Western Reserve University, USA
pp. 29-36
Session 2: Network-on-Chip Reliability and Fault Tolerance

Essential Fault-Tolerance Metrics for NoC Infrastructures (Abstract)

Andre Ivanov , University of British Columbia, Canada
Partha P. Pande , Washington State University
Lorena Anghel , TIMA Laboratory, France
Resve Saleh , University of British Columbia, Canada
Cristian Grecu , University of British Columbia, Canada
pp. 37-42

Configurable Error Control Scheme for NoC Signal Integrity (Abstract)

Cecilia Metra , University of Bologna, Italy
Daniele Rossi , University of Bologna, Italy
Paolo Angelini , University of Bologna, Italy
pp. 43-48

An Analytical Model for Reliability Evaluation of NoC Architectures (Abstract)

Mohammad Hosseinabady , University of Tehran, Iran
Atefe Dalirsani , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 49-56
Session 3: Secure Systems

An On-Line Fault Detection Scheme for SBoxes in Secure Circuits (Abstract)

B. Rouzeyre , Universite Montpellier II, France
M.-L. Flottes , Universite Montpellier II, France
G. Di Natale , Universite Montpellier II, France
pp. 57-62

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding (Abstract)

Francis Wolff , Case Western Reserve University, USA
Chris Papachristou , Case Western Reserve University, USA
Osama Al-Khaleel , Case Western Reserve University, USA
Kiamal Pekmestzi , National Technical University, Greece
pp. 71-78
Session 4: Large Scale Dependability

Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs (Abstract)

Marlon Moraes , Catholic University-PUCRS, Brazil
Leonardo Piccoli , Catholic University-PUCRS, Brazil
Antonio A. de Alecrim Jr. , Catholic University-PUCRS, Brazil
Fabian Vargas , Catholic University-PUCRS, Brazil
Juliano Benfica , Catholic University-PUCRS, Brazil
pp. 93-100
Session 5: Dependability of Processors, SoCs and Asynchronous Circuits

A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors (Abstract)

Marta Portela-Garcia , Carlos III University of Madrid, Spain
Celia L?pez-Ongil , Carlos III University of Madrid, Spain
Luis Entrena , Carlos III University of Madrid, Spain
Mario Garcia-Valderas , Carlos III University of Madrid, Spain
pp. 101-106

A Hybrid Approach to Fault Detection and Correction in SoCs (Abstract)

P. Bernardi , Politecnico di Torino, Italy
L. Bolzani , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 107-112

Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs (Abstract)

Y. Monnet , TIMA Laboratory, France
M. Renaudin , TIMA Laboratory, France
R. Leveugle , TIMA Laboratory, France
pp. 113-120
Special Session 1: Aging and Wearout Issues and Mitigation Approaches
Keynote Talk
Session 6: Radiation Effects

Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs (Abstract)

Tino Heijmen , NXP Semiconductors, The Netherlands
pp. 131-136

Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells (Abstract)

T. Carriere , EADS Astrium Space Transportation
C. Weulerse , EADS, France
N. Buard , EADS, France
F. Wrobel , University of Nice-Sophia Antipolis
N. Renaud , ATMEL
S. Benhammadi , TIMA Laboratory, France
R. Gaillard , INFODUC
L. Anghel , TIMA Laboratory, France
G. Hubert , EADS, France
C. Rusu , TIMA Laboratory, France
A. Bougerol , EADS, France
pp. 137-145

Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions (Abstract)

A. Paccagnella , Padova University, Italy
G. Cellere , Padova University, Italy
S. Beltrami , STMicroelectronics, Italy
M. Maccarrone , STMicroelectronics, Italy
S. Gerardin , Padova University, Italy
A. Visconti , STMicroelectronics, Italy
M. Bagatin , Padova University, Italy
pp. 146-151

On Derating Soft Error Probability Based on Strength Filtering (Abstract)

Alodeep Sanyal , University of Massachusetts at Amherst, USA
Sandip Kundu , University of Massachusetts at Amherst, USA
pp. 152-160
Session 7: Signal Integrity and Error Compensation

Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics (Abstract)

Cristian Grecu , University of British Columbia, Canada
Partha Pratim Pande , Washington State University, USA
Amlan Gangul , Washington State University, USA
Brett Feero , Washington State University, USA
pp. 161-166

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits (Abstract)

J.P. Teixeira , IST/INDESC-ID Lisboa, Portugal
J. Semi? , IST/INDESC-ID Lisboa, Portugal; Univ. of Algarve, Portugal
M.B. Santos , IST/INDESC-ID Lisboa, Portugal
J.J. Rodr?guez-Andina , Univ. of Vigo, Spain
J. Freijedo , IST/INDESC-ID Lisboa, Portugal; Univ. of Vigo, Spain
I.C. Teixeira , IST/INDESC-ID Lisboa, Portugal
F. Vargas , PUCRS, Brazil
pp. 167-172

Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums (Abstract)

Muhammad M. Nisar , Georgia Institute of Technology, USA
Maryam Ashouei , Georgia Institute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 173-182
Session 8: Posters

Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment (PDF)

J. Segura , GET, U. Illes Balears.
S. Bota , GTE, U. Illes Balears
A. Comerma , U. Barcelona, Spain
L. Garrido , U. Barcelona, Spain
A. Herms , U. Barcelona, Spain
R. Graciani , U. Barcelona, Spain
X. Cano , U. Barcelona, Spain
D. Gasc? , U. Barcelona, Spain
pp. 183-184

Robustness of circuits under delay-induced faults : test of AES with the PAFI tool (PDF)

Laurent Freund , Ecole des Mines de St Etienne, France
Assia Tria , CEA-LETI, France
Frederic Bancel , STMicroelectronics, France
Olivier Faurax , Ecole des Mines de St Etienne, France; Universite de la Mediterranee, France
pp. 185-186

Highly Reliable Power Aware Memory Design (PDF)

Costas Argyrides , University of Bristol, UK
Dhiraj K. Pradhan , University of Bristol, UK
pp. 189-190

Accelerating Soft Error Rate Testing Through Pattern Selection (Abstract)

Alodeep Sanyal , University of Massachusetts at Amherst, USA
Kunal Ganeshpure , University of Massachusetts at Amherst, USA
Sandip Kundu , University of Massachusetts at Amherst, USA
pp. 191-193

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders (Abstract)

M. Re , University of Rome "Tor Vergata", Italy
S. Pontarelli , University of Rome "Tor Vergata", Italy
G.C. Cardarilli , University of Rome "Tor Vergata", Italy
A. Salsano , University of Rome "Tor Vergata", Italy
L. Sterpone , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 194-196

Embedding test patterns into Low-Power BIST sequences (PDF)

Ioannis Voyiatzis , Technological Educational Institute of Athens, Greece
pp. 197-198

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes (PDF)

Houssein Jaber , University of Metz, France
Stanislaw J. Piestrak , University of Metz, France
Abbas Dandache , University of Metz, France
Fabrice Monteiro , University of Metz, France
pp. 199-200

Identification of Critical Errors in Imaging Applications (PDF)

Damian Nowroth , Albert-Ludwigs-University, Germany
Illia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 201-202

Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena (PDF)

Franz X. Ruckerbauer , Infineon Technologies AG, Germany
Georg Georgakos , Infineon Technologies AG, Germany
pp. 203-204

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC (PDF)

Mohammad Hosseinabady , University of Tehran, Iran
Alfredo Benso , Politecnico di Torino, Italy
Giorgio Di Natale , LIRMM, France
Paolo Prinetto , Politecnico di Torino, Italy
Stefano Di Carlo , Politecnico di Torino, Italy
M.H. Neishaburi , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 205-206

Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set (PDF)

H. Rahaman , University of Bristol, UK
J. Mathew , University of Bristol, UK
D.K. Pradhan , University of Bristol, UK
pp. 207-208
Session 9: Fault Tolerance

Automated Derivation of Application-aware Error Detectors using Static Analysis (Abstract)

Zbigniew Kalbarczyk , University of Illinois, USA
Ravishankar K. Iyer , University of Illinois, USA
Karthik Pattabiraman , University of Illinois, USA
pp. 211-216

On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs (Abstract)

Gustavo R. Alves , LABORIS/ISEP, Portugal
Luis F. Lemos , LABORIS/ISEP, Portugal
Jose M. Ferreira , FEUP, Portugal
Manuel G. Gericota , LABORIS/ISEP, Portugal
pp. 217-222

A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits (Abstract)

A. Yakovlev , University of Newcastle upon Tyne, UK
K.T. Gardiner , University of Newcastle upon Tyne, UK
A. Bystrov , University of Newcastle upon Tyne, UK
pp. 223-230
Session 10: On-Line Testing for Analog, Mixed-Signal, RF and Delay Defect Tolerance

Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches (Abstract)

S. Mir , TIMA Laboratory, France
R. Kherreddine , TIMA Laboratory, France
H.N. Nguyen , TIMA Laboratory, France
E. Simeu , TIMA Laboratory, France
pp. 237-243

Tolerance to Small Delay Defects by Adaptive Clock Stretching (Abstract)

Swarup Bhunia , Case Western Reserve University, USA
Patrick NDai , Purdue University, USA
Kaushik Roy , Purdue University, USA
Swaroop Ghosh , Purdue University, USA
pp. 244-252
Special Session 3: Fault-Tolerant and Self-Adapting Design to Mitigate Power, Yield and Reliability Issues in Upcoming Process Nodes
Special Session 4: Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips

Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips (PDF)

Piotr Zajac , LAAS-CNRS, France; Technical University of Lodz, Poland
Jacques Henri Collet , LAAS-CNRS, France
pp. 259

Surviving to Errors in Multi-Core Environments (PDF)

Jaume Abella , Intel Barcelona Research Center
Xavier Vera , Intel Barcelona Research Center
pp. 260
Session 11: Processor-Based Testing

An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores (Abstract)

M. Schillaci , Politecnico di Torino, Italy
G. Squillero , Politecnico di Torino, Italy
E. Sanchez , Politecnico di Torino, Italy
L. Bolzani , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 265-270

A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs (Abstract)

A. Apostolakis , University of Piraeus, Greece
A. Paschalis , University of Athens, Greece
D. Gizopoulos , University of Piraeus, Greece
M. Psarakis , University of Piraeus, Greece
pp. 271-276

A Configurable Modular Test Processor and Scan Controller Architecture (Abstract)

D. Rudolph , University of Technology Cottbus, Germany
R. Kothe , University of Technology Cottbus, Germany
R. Frost Brandenburg , University of Technology Cottbus, Germany
C. Galke , University of Technology Cottbus, Germany
H.T. Vierhaus , University of Technology Cottbus, Germany
pp. 277-284
Session 12: Self-Checking and Self-Testing

LFSR Reseeding with Irreducible Polynomials (Abstract)

Dimitri Kagaris , Southern Illinois University, USA
Snehal Udar , Southern Illinois University, USA
pp. 293-298
Author Index

Author Index (PDF)

pp. 299
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