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11th IEEE International On-Line Testing Symposium (2007)
Heraklion, Crete, Greece
July 8, 2007 to July 11, 2007
ISBN: 0-7695-2918-6
pp: 265-270
L. Bolzani , Politecnico di Torino, Italy
E. Sanchez , Politecnico di Torino, Italy
M. Schillaci , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
G. Squillero , Politecnico di Torino, Italy
ABSTRACT
Test of peripheral modules has not yet been deeply investigated by the research community. When embedded in a system on a chip, peripheral cores introduce new issues for post-production testing. A peripheral core embedded in a SoC requires a test set able to properly perform two different tasks: configure the device in different operation modes and properly exercise it. In this paper an automatic approach able to generate test sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The method compares favorably with results obtained by hand.
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CITATION

M. Schillaci, G. Squillero, E. Sanchez, L. Bolzani and M. S. Reorda, "An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores," 11th IEEE International On-Line Testing Symposium(IOLTS), Heraklion, Crete, Greece, 2007, pp. 265-270.
doi:10.1109/IOLTS.2007.14
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