The Community for Technology Leaders
11th IEEE International On-Line Testing Symposium (2006)
Lake of Como, Italy
July 10, 2006 to July 12, 2006
ISBN: 0-7695-2620-9
TABLE OF CONTENTS
Introduction
Introduction
Keynote Talk
Invited Talk
Session 1: Fault Effects and Self-Checking Techniques

Characterizing Laser-Induced Pulses in ICs: Methodology and Results (Abstract)

S. J. Piestrak , University of Metz, France
A. Dandache , University of Metz, France
S. Rossignol , iRoC Technologies SA
F. Monteiro , University of Metz, France
P. Moitrel , Gemplus
D. Leroy , iRoC Technologies SA
pp. 11-16

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits? Operation (Abstract)

J. M. Cazeaux , University of Bologna, Italy
D. Rossi , University of Bologna, Italy
M. Oma? , University of Bologna, Italy
C. Metra , University of Bologna, Italy
TM Mak , Intel Corporation, USA
pp. 17-22

A New Self-Checking and Code-Disjoint Non-Restoring Array Divider (Abstract)

V. Otcheretnij , University of Potsdam, Germany
D. Marienfeld , University of Potsdam, Germany
M. G?ssel , University of Potsdam, Germany
E. S. Sogomonyan , University of Potsdam, Germany
pp. 23-30
Session 2: BIST Techniques

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor (Abstract)

Swaroop Ghosh , Purdue University, USA
Arijit Raychowdhury , Purdue University, USA
Swarup Bhunia , Purdue University, USA
Kaushik Roy , Purdue University, USA
pp. 31-36

A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST (Abstract)

Irith Pomeranz , Purdue University, USA
Chaowen Yu , University of Iowa, USA
Sudhakar M. Reddy , University of Iowa, USA
pp. 37-42

Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding (Abstract)

Maria K. Michael , University of Cyprus, Cyprus
Stelios Neophytou , University of Cyprus, Cyprus
Spyros Tragoudas , Southern Illinois University, USA
pp. 43-50
Session 3: Technology Robustness

Erratic Effects of Irradiation in Floating Gate Memory Cells (Abstract)

G. Cellere , Padova University, Italy
A. Paccagnella , Padova University, Italy
A. Visconti , STMicroelectronics, Italy
M. Bonanomi , STMicroelectronics, Italy
pp. 51-56

Factors That Impact the Critical Charge of Memory Elements (Abstract)

Damien Giot , ST Microelectronics, France
Philippe Roche , ST Microelectronics, France
Tino Heijmen , Philips Research Laboratories (WAY41), The Netherlands
pp. 57-62

Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells (Abstract)

N. Buard , EADS, Corporate Research Center
A. Bougerol , EADS, Corporate Research Center
F. Miller , EADS, Corporate Research Center
R. Gaillard , INFODUC
L. Anghel , TIMA Laboratory
F. Wrobel , University of Nice-Sophia Antipolis
G. Hubert , EADS, Corporate Research Center
T. Carriere , EADS, Space Transportation
pp. 63-74
Special Session 1: Memory Reliability Challenges

Towards The Methodology of On-line Diagnosis (PDF)

Rochit Rajsuman , Advantest America Corporation, USA
pp. 76
Special Session 2: Test and Reliability Challenges for Innovative Systems

Test Challenges for 3D Circuits (PDF)

TM Mak , Intel Corporation
pp. 79
Panel 1
Embedded Tutorials: Innovative Design for Robustness

Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility (Abstract)

Melanie Berg , NASA Goddard Space Flight Center Radiation Effects and Analysis Group/MEI Technologies
pp. 89-91

Asynchronous Design: Fault Robustness and Security Characteristics (Abstract)

Marc Renaudin , TIMA Laboratory, France
Yannick Monnet , TIMA Laboratory, France
pp. 92-95
Session 4: Soft Errors and Latchup Mitigation

Combinational Logic Soft Error Analysis and Protection (Abstract)

Andre K. Nieuwland , Philips Research Eindhoven, Netherlands
Samir Jasarevic , Philips Semiconductors, UK
Goran Jerin , Lund University, Sweden
pp. 99-104

An Improved Technique for Reducing False Alarms Due to Soft Errors (Abstract)

Ilia Polian , Albert-Ludwigs-University of Freiburg, Germany
Sandip Kundu , University of Massachusets, USA
pp. 105-110

A Low-Cost Single-Event Latchup Mitigation Sscheme (Abstract)

Michael Nicolaidis , TIMA Laboratory, France
pp. 111-118
Session 5: Secure Circuits

Secure Scan Techniques: A Comparison (Abstract)

Marie-Lise Flottes , Universit? Montpellier II, France
Bruno Rouzeyre , Universit? Montpellier II, France
Fr?d?ric Bancel , ST Microelectronics, France
David H?ly , ST Microelectronics, France
pp. 119-124

Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor (Abstract)

R. Leveugle , TIMA Laboratory, France
P. Moitrel , Gemplus Card International, France
Y. Monnet , TIMA Laboratory, France
F. M'Buwa Nzenguet , Gemplus Card International, France
M. Renaudin , TIMA Laboratory, France
N. Feyt , Gemplus Card International, France
pp. 125-130

Power Attacks on Secure Hardware Based on Early Propagation of Data (Abstract)

Mark G. Karpovsky , Boston University, USA
Alexander Taubin , Boston University, USA
Konrad J. Kulikowski , Boston University, USA
pp. 131-138
Session 6: Fault Detection Techniques

On-line Fault Detection and Location for NoC Interconnects (Abstract)

Cristian Grecu , University of British Columbia, Canada
Partha Pratim Pande , Washington State University, USA
Res Saleh , University of British Columbia, Canada
Andr? Ivanov , University of British Columbia, Canada
Egor S. Sogomonyan , University of Potsdam, Germany
pp. 145-150

CEDA: Control-flow Error Detection through Assertions (Abstract)

Ramtilak Vemu , University of Texas at Austin, USA
Jacob A. Abraham , University of Texas at Austin, USA
pp. 151-158
Session 7: Analog Circuits Dependability

On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data (Abstract)

G. Srinivasan , Georgia Institute of Technology
V. Natarajan , Georgia Institute of Technology
A. Chatterjee , Georgia Institute of Technology
pp. 159-164
Session 8: Posters

Embedded Borden 2-UED Code Checkers (Abstract)

Steffen Tarnick , 4TECH GmbH, Germany
pp. 173-175

A Note on Error Detection in an RSA Architecture by Means of Residue Codes (PDF)

L. Breveglieri , Politecnico di Milano, Italy
I. Koren , Univ. of Massachusetts, USA
P. Maistri , Politecnico di Milano, Italy
pp. 176-177

Localization of Faults in Radix-n Signed Digit Adders (Abstract)

M. Re , University of Rome "Tor Vergata", Italy
S. Pontarelli, , University of Rome "Tor Vergata", Italy
M. Ottavi , University of Rome "Tor Vergata", Italy
G.C. Cardarilli , University of Rome "Tor Vergata", Italy
A. Salsano , University of Rome "Tor Vergata", Italy
pp. 178-180

Embedded Scan Test with Diagnostic Features for Self-Testing SoCs (PDF)

S. Schultke , Brandenburg University of Technology Cottbus
K. Winkler , Brandenburg University of Technology Cottbus
C. Galke , Brandenburg University of Technology Cottbus
H. T. Vierhaus , Brandenburg University of Technology Cottbus
J. Honko , Brandenburg University of Technology Cottbus
R. Kothe , Brandenburg University of Technology Cottbus
pp. 181-182

Emulation-based Fault Injection in Circuits with Embedded Memories (PDF)

Celia L?pez-Ongil , Carlos III University of Madrid. Spain
Luis Entrena , Carlos III University of Madrid. Spain
Marta Portela-Garc? , Carlos III University of Madrid. Spain
Mario Garc?a-Valderas , Carlos III University of Madrid. Spain
pp. 183-184

Fault Tolerant System Design Method Based on Self-Checking Circuits (PDF)

Hana Kub?tov? , Czech Technical University in Prague, Czech Republic
Pavel Kubal? , Czech Technical University in Prague, Czech Republic
Petr Fiser , Czech Technical University in Prague, Czech Republic
pp. 185-186

Built-in Self Repair by Reconfiguration of FPGAs (PDF)

S. Habermann , Brandenburg University of Technology Cottbus, Germany
R. Kothe , Brandenburg University of Technology Cottbus, Germany
H. T. Vierhaus , Brandenburg University of Technology Cottbus, Germany
pp. 187-188

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices (PDF)

M. Violante , Politecnico di Torino, Italy
L. Sterpone , Politecnico di Torino, Italy
pp. 189-190

Diophantine-Equation Based Arithmetic Test Set Embedding (PDF)

D. Nikolos , University of Patras, Greece
D. Kagaris , Southern Illinois University, USA
S. Gidaros , University of Patras, Greece
pp. 193-194

Design of a Robust 8-Bit Microprocessor to Soft Errors (PDF)

Rodrigo Possamai Bastos , Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
Ricardo Reis , Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
pp. 195-196
Panel 2

Should Logic SER be Solved at the Circuit Level? (PDF)

S. Mitra , Stanford University
T. M. Mak , Intel Corporation
pp. 199
Session 9: Reliable Systems

Fault-Robust Microcontrollers for Automotive Applications (Abstract)

Riccardo Mariani , YOGITECH SpA
Boris Vittorelli , ARM Germany GmbH
Peter Fuhrmann , Philips Research Laboratories
pp. 213-218

Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures (Abstract)

Yves Crouzet , Universit? de Toulouse, France
Piotr Zajac , Technical University of Lodz, Poland
Jacques Henri Collet , Universit? de Toulouse, France
Andrzej Napieralski , Technical University of Lodz, Poland
pp. 219-228
Session 10: Dependability Analysis

Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 229-234

A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs (Abstract)

N. Kranitis , University of Athens, Greece
A. Paschalis , University of Athens, Greece
M. Psarakis , University of Piraeus, Greece
D. Gizopoulos , University of Piraeus, Greece
P. Kenterlis , University of Athens, Greece
pp. 235-241

Real Time Fault Injection Using a Modified Debugging Infrastructure (Abstract)

Gustavo R. Alves , Instituto Superior de Engenharia do Porto, Portugal
Andr? V. Fidalgo , Instituto Superior de Engenharia do Porto, Portugal
Jos? M. Ferreira , Faculdade de Engenharia da Universidade do Porto, Portugal
pp. 242-250
Session 11: New Topics in Fault Detection

The Problem of On-Line Testing Methods In Approximate Data Processing (Abstract)

J. Drozd , Odessa National Polytechnic University, Ukraine
M. Lobachev , Odessa National Polytechnic University, Ukraine
A. Drozd , Odessa National Polytechnic University, Ukraine
pp. 251-256

Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes (Abstract)

J. Semi? , INESC-ID / Univ. Algarve, Portugal
I.C. Teixeira , IST/INESC-ID Lisboa, Portugal
J.P. Teixeira , IST/INESC-ID Lisboa, Portugal
M. Rodr?guez-Irago , IST/INESC-ID Lisboa, Portugal
J.J. Rodr?guez Andina , Univ. of Vigo, Spain
F. Vargas , PUCRS, Brazil
pp. 257-262

Online Testing by Protocol Decomposition (Abstract)

Alex Bystrov , University of Newcastle upon Tyne, UK
Alex Yakovlev , University of Newcastle upon Tyne, UK
Deepali Koppad , University of Newcastle upon Tyne, UK
Danil Sokolov , University of Newcastle upon Tyne, UK
pp. 263-268
Panel 3
Special Session 3: SER Trends: Vision and Developments from European IDMs

Soft Error Rates in Deep-Submicron CMOS Technologies (PDF)

Tino Heijmen , Philips Research Laboratories, The Netherlands
pp. 271

Trend in DRAM Soft Errors (PDF)

G?nter Schindlbeck , Infineon Technologies
pp. 272
Session 12: Checkers and Error Correction

Checker No-Harm Alarm Robustness (Abstract)

Daniele Rossi , D.E.I.S. University of Bologna, Italy
Martin x Martin Oma? , D.E.I.S. University of Bologna, Italy
Andrea Pagni , STMicroelectronics, Italy
Cecilia Metra , D.E.I.S. University of Bologna, Italy
pp. 275-280

Designing Robust Checkers in the Presence of Massive Timing Errors (Abstract)

Frederic Worm , Ecole Polytechnique F?ed?erale de Lausanne
Patrick Thiran , Ecole Polytechnique F?ed?erale de Lausanne
Paolo Ienne , Ecole Polytechnique F?ed?erale de Lausanne
pp. 281-286

Error Correction in Arithmetic Operations by I/O Inversion (Abstract)

Petros Oikonomakos , University of Cambridge, UK
Paul Fox , University of Cambridge, UK
pp. 287-292
Author Index

Author Index (PDF)

pp. 293-294
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