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11th IEEE International On-Line Testing Symposium (2006)
Lake of Como, Italy
July 10, 2006 to July 12, 2006
ISBN: 0-7695-2620-9
pp: 17-22
J. M. Cazeaux , University of Bologna, Italy
D. Rossi , University of Bologna, Italy
M. Oma? , University of Bologna, Italy
C. Metra , University of Bologna, Italy
TM Mak , Intel Corporation, USA
ABSTRACT
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths? max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or wear out in the field would potentially also cripple the clock distribution network. Consequently, we should start considering also path (min) delay faults when designing on-line testable circuits, similar to what we currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults.
INDEX TERMS
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CITATION
J. M. Cazeaux, D. Rossi, M. Oma?, C. Metra, TM Mak, "Path (Min) Delay Faults and Their Impact on Self-Checking Circuits? Operation", 11th IEEE International On-Line Testing Symposium, vol. 00, no. , pp. 17-22, 2006, doi:10.1109/IOLTS.2006.47
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