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11th IEEE International On-Line Testing Symposium (2005)
Saint Raphael, French Riviera, France
July 6, 2005 to July 8, 2005
ISSN: 1530-1591
ISBN: 0-7695-2406-0

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Session 1: Transient Fault Modeling and Analysis

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Electrical Modeling for Laser Testing with Different Pulse Durations (Abstract)

A. Douin , Universit? Bordeaux 1
V. Pouget , Universit? Bordeaux 1
D. Lewis , Universit? Bordeaux 1
P. Fouillat , Universit? Bordeaux 1
P. Perdu , CNES
pp. 9-13

Analyzing the Effectiveness of Fault Hardening Procedures (Abstract)

P. Gawkowski , Warsaw University of Technology
J. Sosnowski , Warsaw University of Technology
B. Radko , Warsaw University of Technology
pp. 14-19
Session 2: Transient Faults' Hardening Techniques

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On Transistor Level Gate Sizing for Increased Robustness to Transient Faults (Abstract)

J. M. Cazeaux , University of Bologna
D. Rossi , University of Bologna
M. Omaña , University of Bologna
C. Metra , University of Bologna
A. Chatterjee , Georgia Institute of Technology
pp. 23-28

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study (Abstract)

Cristiano Lazzari , Institute National Polytechnique de Grenoble
Lorena Anghel , Institute National Polytechnique de Grenoble
Ricardo A. L. Reis , Universidade Federal do Rio Grande do Sul
pp. 29-34

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits (Abstract)

Yuvraj S. Dhillon , Georgia Institute of Technology
Abdulkadir U. Diril , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
Cecilia Metra , University of Bologna
pp. 35-40
Session 3: SEU Effects in FPGAs

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Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading (Abstract)

Celia L?pez-Ongil , Carlos III University of Madrid
Mario Garc?a-Valderas , Carlos III University of Madrid
Marta Portela-Garc? , Carlos III University of Madrid
Luis Entrena-Arrontes , Carlos III University of Madrid
pp. 43-48

Heavy Ion Effects on Configuration Logic of Virtex FPGAs (Abstract)

M. Alderighi , IASF, INAF
F. Casini , Sanitas EG, s.r.l.
S. D'Angelo , IASF, INAF
M. Mancini , IASF, INAF
A. Paccagnella , Universit? of Padova
S. Pastore , Sanitas EG, s.r.l.
G. R. Sechi , IASF, INAF
pp. 49-53

Efficient Estimation of SEU Effects in SRAM-Based FPGAs (Abstract)

M. Sonza Reorda , Politecnico di Torino
L. Sterpone , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 54-59
Special Session 1: Robust Design Techniques for Soft Errors

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Impact of Soft Error Challenge on SoC Design (Abstract)

Y. Zorian , Virage Logic Corporation
V. A. Vardanian , Virage Logic Yerevan Branch
K. Aleksanyan , Virage Logic Yerevan Branch
K. Amirkhanyan , Virage Logic Yerevan Branch
pp. 63-68

DFT Assisted Built-In Soft Error Resilience (PDF)

T. M. Mak , Intel Corporation
Subhasish Mitra , Intel Corporation
Ming Zhang , Intel Corporation
pp. 69
Special Session 2: Simulation and Mitigation of Single Event Effects

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A Review of DASIE Code Family: Contribution to SEU/MBU Understanding (Abstract)

G. Hubert , EADS, Corporate Research Center
N. Buard , EADS, Corporate Research Center
C. Weulersse , EADS, Corporate Research Center
T. Carriere , EADS, Space Transportation
M.-C. Palau , EADS, Space Transportation
J.-M. Palau , University of Montpellier
D. Lambert , CEA/DAM
J. Baggio , CEA/DAM
F. Wrobel , University of Nice
F. Saigne , University of Montpellier
R. Gaillard , NFODUC
pp. 87-94
Special Session 3: Self Calibrating Design

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Self Calibrating Circuit Design for Variation Tolerant VLSI Systems (Abstract)

Chris H. Kim , University of Minnesota
Steven Hsu , Intel Corporation, Purdue University
Ram Krishnamurthy , Intel Corporation, Purdue University
Shekhar Borkar , Intel Corporation, Purdue University
Kaushik Roy , Intel Corporation, Purdue University
pp. 100-105

On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST) (Abstract)

Donghoon Han , Georgia Institute of Technology
Selim Sermet Akbay , Georgia Institute of Technology
S. Bhattacharya , Georgia Institute of Technology
A. Chatterjee , Georgia Institute of Technology
William R. Eisenstadt , University of Florida
pp. 106-111
Special Session 4: Secure Implementations

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Side-Channel Issues for Designing Secure Hardware Implementations (Abstract)

Lejla Batina , Katholieke Universiteit Leuven
Nele Mentens , Katholieke Universiteit Leuven
Ingrid Verbauwhede , Katholieke Universiteit Leuven
pp. 118-121
Session 4: On-Line Testing for Secure and Asynchronous Chips

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Hardening Techniques against Transient Faults for Asynchronous Circuits (Abstract)

Y. Monnet , TIMA laboratory
M. Renaudin , TIMA laboratory
R. Leveugle , TIMA laboratory
pp. 129-134

On-Line Testing of Globally Asynchronous Circuits (Abstract)

D. Shang , University of Newcastle upon Tyne
A. Bystrov , University of Newcastle upon Tyne
A. Yakovlev , University of Newcastle upon Tyne
D. Koppad , University of Newcastle upon Tyne
pp. 135-140

On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations (Abstract)

V. Ocheretnij , University of Potsdam
G. Kouznetsov , University of Potsdam
R. Karri , Polytechnic University
M. G?ssel , University of Potsdam
pp. 141-146
Session 5: Self Checking Strategies

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Fast, Parallel Two-Rail Code Checker with Enhanced Testability (Abstract)

S. Matakias , University of Athens
Y. Tsiatouhas , University of Ioannina
Th. Haniotakis , Southern Illinois University
A. Arapoyanni , University of Athens
A. Efthymiou , University of Athens
pp. 149-156

Power-Balanced Self Checking Circuits for Cryptographic Chips (Abstract)

Julian Murphy , University of Newcastle upon Tyne
Alex Bystrov , University of Newcastle upon Tyne
Alex Yakovlev , University of Newcastle upon Tyne
pp. 157-162

On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization (Abstract)

M. Oma? , University of Bologna
O. Losco , University of Bologna
C. Metra , University of Bologna
A. Pagni , STMicroelectronics
pp. 163-168
Session 6: Process Variations, Leakage, and Power Supply Noise Detection and Tolerance

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Process Variation Tolerant Online Current Monitor for Robust Systems (Abstract)

Qikai Chen , Purdue University
Saibal Mukhopadhyay , Purdue University
Hamid Mahmoodi , Purdue University
Kaushik Roy , Purdue University
pp. 171-176

A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits (Abstract)

B. Alorda , Université des les Illes Balears
S. Bota , Université des les Illes Balears
J. Segura , Université des les Illes Balears
pp. 177-182

Coding Techniques for Low Switching Noise in Fault Tolerant Busses (Abstract)

André K. Nieuwland , Philips Research Laboratories
Atul Katoch , Philips Research Laboratories
Daniele Rossi , University of Bologna
Cecilia Metra , University of Bologna
pp. 183-189
Session 7: Posters

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Modeling of Transients Caused by a Laser Attack on Smart Cards (PDF)

Damien Leroy , iRoC Technologies SA
Stanisław J. Piestrak , University of Metz
Fabrice Monteiro , University of Metz
Abbas Dandache , University of Metz
pp. 193-194

A Software Based Online Memory Test for Highly Available Systems (PDF)

Amandeep Singh , Sun Microsystems, Inc.
Debashish Bose , Sun Microsystems, Inc.
pp. 199-200

Design of a Self Checking Reed Solomon Encoder (PDF)

G. C. Cardarilli , University of Rome "Tor Vergata"
S. Pontarelli , University of Rome "Tor Vergata"
M. Re , University of Rome "Tor Vergata"
A. Salsano , University of Rome "Tor Vergata"
pp. 201-202

On the Proposition of an EMI-Based Fault Injection Approach (PDF)

F. Vargas , Catholic University - PUCRS
D. L. Cavalcante , Catholic University - PUCRS
E. Gatti , Instituto Nacional de Tecnologia Industrial
D. Prestes , Catholic University - PUCRS
D. Lupi , Instituto Nacional de Tecnologia Industrial
pp. 207-208

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On-Line Testing for Secure Implementations: Design and Validation (PDF)

Regis Leveugle , Tima Laboratory
Yervant Zorian , Virage Logic
L. Breveglieri , Politechnic di Milano
R. Leveugle , TIMA Laboratory
A. Nieuwland , Philips
K. Rothbart , Technical University of Graz
J. P. Seifert , Intel Inc.
pp. 211
Session 8: Testing Issues

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Accumulator-Based Weighted Pattern Generation (Abstract)

I. Voyiatzis , Technological Educational Institute of Athens
D. Gizopoulos , University of Piraeus
A. Paschalis , University of Athens
pp. 215-220

A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage (Abstract)

Dhiraj K. Pradhan , University of Bristol
Dimitri Kagaris , Southern Illinois University
Rohit Gambhir , Southern Illinois University
pp. 221-226

Test Generation Methodology for High-Speed Floating Point Adders (Abstract)

G. Xenoulis , University of Piraeus
M. Psarakis , University of Piraeus
D. Gizopoulos , University of Piraeus
A. Paschalis , University of Athens
pp. 227-232
Session 9: SoC Testing and Fault Tolerance

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Integrating BIST Techniques for On-Line SoC Testing (Abstract)

A. Manzone , Centro Ricerche Fiat
P. Bernardi , Politecnico di Torino
M. Grosso , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
E. Sanchez , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 235-240

A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features (Abstract)

R. Kothe , Brandenburg University of Technology Cottbus
C. Galke , Brandenburg University of Technology Cottbus
H. T. Vierhaus , Brandenburg University of Technology Cottbus
pp. 241-246
Session 10: Multiple Bit Upset Evaluation and Correction

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Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators (Abstract)

Erik Sch? , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. 255-259

Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM (Abstract)

Balkaran Gill , Case Western Reserve University
Michael Nicolaidis , IROC Technologies
Chris Papachristou , Case Western Reserve University
pp. 266-271
Session 11: Timing, Yield, and Reliability Issues

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Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test (Abstract)

M. Rodriguez-Irago , IST/INESC-ID Lisboa and University of Vigo
J. J. Rodriguez Andina , University of Vigo
F. Vargas , PUCRS
M. B. Santos , IST/INESC-ID Lisboa
I. C. Teixeira , IST/INESC-ID Lisboa
J. P. Teixeira , IST/INESC-ID Lisboa
pp. 281-286

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning (Abstract)

A. Raychowdhury , Purdue University
S. Ghosh , Purdue University
K. Roy , Purdue University
pp. 287-292
Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing

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Overview of Soft Errors Issues in Aerospace Systems (Abstract)

Christian Bol?at , Astrium EADS
G?rard Colas , Thales Avionics
pp. 299-302

Evaluation of SET and SEU Effects at Multiple Abstraction Levels (Abstract)

L. Anghel , TIMA Laboratory
R. Leveugle , TIMA Laboratory
P. Vanhauwaert , TIMA Laboratory
pp. 309-312
Author Index

Author Index (PDF)

pp. 325-326
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