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11th IEEE International On-Line Testing Symposium (2004)
Funchal, Madeira Island, Portugal
July 12, 2004 to July 14, 2004
ISBN: 0-7695-2180-0
TABLE OF CONTENTS

TTTC Information (PDF)

pp. 249
Opening Session-Keynote Talk
Session 1: Timing and Transient Faults

Modeling and Simulation of Time Domain Faults in Digital Systems (Abstract)

F. Vargas , PUCRS, Porto Alegre, Brazil
J. P. Teixeira , IST / INESC-ID Lisboa, Portugal
M. B. Santos , IST / INESC-ID Lisboa, Portugal
D. Barros J?nior , PUCRS, Porto Alegre, Brazil
I. C. Teixeira , IST / INESC-ID Lisboa, Portugal
pp. 5

Sizing CMOS Circuits for Increased Transient Error Tolerance (Abstract)

Yuvraj S. Dhillon , Georgia Institute of Technology, Atlanta, GA
Abdulkadir U. Diril , Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Adit D. Singh , Auburn University, Auburn, AL
pp. 11

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop (Abstract)

Cecilia Metra , D.E.I.S. University of Bologna, Italy
Jos? Manuel Cazeaux , D.E.I.S. University of Bologna, Italy
Martin Oma? , D.E.I.S. University of Bologna, Italy
pp. 17
Session 2: Self Testing and Self Checking Circuits

Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits (Abstract)

M. G?ssel , University of Potsdam
A. Morozov , University of Potsdam
V. Saposhnikov , Petersburg State Transport University
Vl. Saposhnikov , Petersburg State Transport University
pp. 25

Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits (Abstract)

E. S. Sogomonyan , University of Potsdam, Germany
D. Marienfeld , University of Potsdam, Germany
M. G?ssel , University of Potsdam, Germany
V. Ocheretnij , University of Potsdam, Germany
pp. 31

A Hierarchical Self Test Scheme for SoCs (Abstract)

Claudia Kretzschmar , Brandenburg University of Technology Cottbus, Germany
Christian Galke , Brandenburg University of Technology Cottbus, Germany
Heinrich T. Vierhaus , Brandenburg University of Technology Cottbus, Germany
pp. 37
Session 3: Checker and Voter Design

A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations (Abstract)

A. Rao , Southern Illinois University, USA
V. Kaky , Southern Illinois University, USA
Th. Haniotakis , Southern Illinois University, USA
Y. Tsiatouhas , University of Ioannina, Greece
pp. 52

New High Speed CMOS Self-Checking Voter (Abstract)

Daniele Rossi , D.E.I.S. University of Bologna, Italy
Cecilia Metra , D.E.I.S. University of Bologna, Italy
Jos? Manuel Cazeaux , D.E.I.S. University of Bologna, Italy
pp. 58
Session 4: Concurrent Error Detection

Low Cost On-Line Testing of RF Circuits (Abstract)

Altamiro A. Susin , Universidade Federal do Rio Grande do Sul, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul, Brazil
pp. 73

Hybrid Soft Error Detection by Means of Infrastructure IP Cores (Abstract)

L. Bolzani , Pontif?cia Universidade Cat?lica do Rio Grande do Sul (PUCRS), Brazil
M. Sonza Reorda , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
F. Vargas , Politecnico di Torino, Italy
pp. 79
Panel Session 1: On Emerging Field Reliability and Dependability Challenges

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Session 5: Microprocessor On-Line Testing

A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors (Abstract)

P. D. Hyde , University of Newcastle upon Tyne, UK
G. Russell , University of Newcastle upon Tyne, UK
pp. 89

Testing of Hard Faults in Simultaneous Multithreaded Processors (Abstract)

Kewal K. Saluja , University of Wisconsin - Madison
Eric F. Weglarz , University of Wisconsin - Madison
T. M. Mak , Intel Corporation, Santa Clara, CA
pp. 95

Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm (Abstract)

Hamid Sarbazi-Azad , Sharif University of Technology; Institute for Studies in Theoretical Physics & Maths (IPM)
Seyed Ghassem Miremadi , Sharif University of Technology
Hamid R. Zarandi , Sharif University of Technology
pp. 101
Session 6: On-Line Testing Evaluation

Transient Fault Emulation of Hardened Circuits in FPGA Platforms (Abstract)

Celia L?pez-Ongil , University Carlos III of Madrid, Spain
Luis Entrena-Arrontes , University Carlos III of Madrid, Spain
Mario Garc?a-Valderas , University Carlos III of Madrid, Spain
Marta Portela-Garc? , University Carlos III of Madrid, Spain
pp. 109

On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs (Abstract)

P. Bernardi , Politecnico di Torino, Italy
L. Sterpone , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 115

Asynchronous Circuits Sensitivity to Fault Injection (Abstract)

R. Leveugle , TIMA laboratory, France
Y. Monnet , TIMA laboratory, France
M. Renaudin , TIMA laboratory, France
pp. 121
Session 7: Error Correcting Code Based Fault Tolerance

Designing a High Speed Decoder for Cyclic Codes (Abstract)

A. Dandache , LICM/CESIUM, University of Metz, France
B. Lepley , LICM/CESIUM, University of Metz, France
F. Monteiro , LICM/CESIUM, University of Metz, France
A. M'Sir , LICM/CESIUM, University of Metz, France
pp. 129

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems (Abstract)

A. K. Nieuwland , Philips Research Laboratories, The Netherlands
C. Metra , DEIS, University of Bologna, Italy
A. Katoch , Philips Research Laboratories, The Netherlands
A. Muccio , DEIS, University of Bologna, Italy
D. Rossi , DEIS, University of Bologna, Italy
pp. 135

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities (Abstract)

G. C. Cardarilli , University of Rome "Tor Vergata", Italy
S. Pontarelli , University of Rome "Tor Vergata", Italy
A. Salsano , University of Rome "Tor Vergata", Italy
M. Ottavi , University of Rome "Tor Vergata", Italy
M. Re , University of Rome "Tor Vergata", Italy
pp. 141
Session 8: Reconfiguration, Repair, and Reuse for Fault Tolerance

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Amit Agarwal , Purdue University, West Lafayette, IN
Bipul C. Paul , Purdue University, West Lafayette, IN
pp. 149

Hardware Reconfiguration Scheme for High Availability Systems (Abstract)

A. Pagni , STMicroelectronics (Italy)
C. Metra , DEIS-U. of Bologna
M. Oma? , DEIS-U. of Bologna
A. Ferrari , DEIS-U. of Bologna
pp. 161

Operating System Function Reuse to Achieve Low-Cost Fault Tolerance (Abstract)

Portolan Michele , TIMA Laboratory, France
Leveugle R?gis , TIMA Laboratory, France
pp. 167
Session 9: Posters

A New Code with Reduced EMI and Partial EC Possibilities (PDF)

E. Dilger , Robert Bosch Company, Stuttgart, Germany
E. B? , Robert Bosch Company, Stuttgart, Germany
M. B? , Robert Bosch Company, Stuttgart, Germany
pp. 175

A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits (PDF)

Ian Grout , University of Limerick, Ireland
Thomas O'Shea , University of Limerick, Ireland
pp. 176

Automated Logic SER Analysis and On-Line SER reduction (PDF)

Patrick Gindner , University of Karlsruhe, Germany
Andr? K. Nieuwland , Philips Research Laboratories, The Netherlands
pp. 177

On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA (PDF)

R. Picos , Universitat de les Illes Balears, Spain
E. Isern , Universitat de les Illes Balears, Spain
S. A. Bota , Universitat de les Illes Balears, Spain
M. Roca , Universitat de les Illes Balears, Spain
E. Garc? , Universitat de les Illes Balears, Spain
pp. 179

An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets (PDF)

L. Carro , Instituto de Inform?tica and Departamento de Engenharia El?trica - UFRGS
C. A. L. Lisb? , Instituto de Inform?tica and Departamento de Engenharia El?trica - UFRGS
pp. 180

Survey of the Algorithms in the Column-Matching BIST Method (PDF)

Petr Fiser , Czech Technical University
Hana Kubatova , Czech Technical University
pp. 181

A Technique to Reduce Power and Test Application Time in BIST (PDF)

Swarup Bhunia , Purdue University, West Lafayette, Indiana
Kaushik Roy , Purdue University, West Lafayette, Indiana
Debjyoti Ghosh , Purdue University, West Lafayette, Indiana
pp. 182

Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits (PDF)

Siddhartha Mukhopadhyay , Indian Institute of Technology, Kharagpur, India
Amit Patra , Indian Institute of Technology, Kharagpur, India
Santosh Biswas , Indian Institute of Technology, Kharagpur, India
pp. 184
Session 10: Built In Self Test

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs (Abstract)

Michel Renovell , Universit? Montpellier II / CNRS, France
Olivier H?ron , Universit? Montpellier II / CNRS, France
Serge Pravossoudovitch , Universit? Montpellier II / CNRS, France
Patrick Girard , Universit? Montpellier II / CNRS, France
pp. 187

Accumulator based Test-per-Scan BIST (Abstract)

D. Kagaris , Southern Illinois University, Carbondale
D. Nikolos , University of Patras, Greece; Computer Technology Institute, Greece
P. Karpodinis , University of Patras, Greece; Computer Technology Institute, Greece
pp. 193

A BIST-based Charge Analysis for Embedded Memories (Abstract)

J. Segura , Univ. de les Illes Balears
B. Alorda , Univ. de les Illes Balears
V. Canals , Univ. de les Illes Balears
I. de Pa? , Univ. de les Illes Balears
pp. 199
Session 11: Safety and Security

A System for Fault Detection and Reconfiguration of Hardware Based Active Networks (Abstract)

Alexandros G. Fragkiadakis , Loughborough University, UK
David J. Parish , Loughborough University, UK
Nikolaos G. Bartzoudis , Loughborough University, UK
Jos? Luis N? , Loughborough University, UK
pp. 207

Fault Tolerant Mechatronics (Abstract)

Roland Karrelmeyer , Robert Bosch GmbH, Stuttgart, Germany
Bernd Straube , Fraunhofer-Institut f?r Integrierte Schaltungen, Dresden, Germany
Elmar Dilger , Robert Bosch GmbH, Stuttgart, Germany
pp. 214

Scan Design and Secure Chip (Abstract)

Bruno Rouzeyre , LIRMM - UMII, France
David H?ly , ST Microelectronics, France
Marie-Lise Flottes , LIRMM - UMII, France
Fr?d?ric Bancel , ST Microelectronics, France
Michel Renovell , LIRMM - UMII, France
Nicolas B?rard , ST Microelectronics, France
pp. 219
Session 12: Dependability Evaluation

On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation (Abstract)

K. Hadjiat , TIMA Laboratory, France
A. Ammari , TIMA Laboratory, France
R. Leveugle , TIMA Laboratory, France
pp. 227

Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique (Abstract)

R. Velazco , TIMA Laboratory, France
B. Nicolescu , Ecole Polytechnique de Montr?al, Canada
Y. Savaria , Ecole Polytechnique de Montr?al, Canada
pp. 233

Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection (Abstract)

Amir Rajabzadeh , Sharif University of Technology, Tehran, Iran
Seyed Ghassem Miremadi , Sharif University of Technology, Tehran, Iran
Mirzad Mohandespour , Sharif University of Technology, Tehran, Iran
pp. 239
Panel Session 2: Reliability Implications of Statistical Design

Author Index (PDF)

pp. 247
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