The Community for Technology Leaders
2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2005)
San Francisco, USA
Feb. 13, 2005 to Feb. 13, 2005
ISSN: 1550-6207
ISBN: 0-7695-2321-8
TABLE OF CONTENTS
I. Compiling for CMP

Compiler Analysis for Trace-Level Speculative Multithreaded Architectures (Abstract)

Jordi Tubella , Universitat Politècnica de Catalunya, Spain
Carlos Molina , Universitat Rovira i Virgili, Spain
Antonio Gonzalez , Universitat Politècnica de Catalunya, Spain; Intel Labs-Univ. Politècnica de Catalunya, Spain
pp. 2-10

Multigrain Parallel Processing on Compiler Cooperative Chip Multiprocessor (Abstract)

Hirufumi Nakano , Dept. of Computer Science Waseda University, Japan
Hironori Kasahara , Dept. of Computer Science Waseda University, Japan
Kazuhisa Ishizaka , Dept. of Computer Science Waseda University, Japan
Keiji Kimura , Dept. of Computer Science Waseda University, Japan
Jun Shirako , Dept. of Computer Science Waseda University, Japan
Yasutaka Wada , Dept. of Computer Science Waseda University, Japan
Takeshi Kodaka , Dept. of Computer Science Waseda University, Japan
pp. 11-20
II. Compiling for Itanium Architecture

An Empirical Study of Data Speculation Use on the Intel Itanium 2 Processor (Abstract)

Jose Baiocchi , University of Pittsburgh, Pittsburgh, PA
Ricardo Villamarin , University of Pittsburgh, Pittsburgh, PA
Markus Mock , University of Pittsburgh, Pittsburgh, PA
pp. 22-33

Analyis of Path Profiling Information Generated with Performance Monitoring Hardware (Abstract)

Vijay Janapa Reddi , University of Colorado at Boulder
Alex Shye , University of Colorado at Boulder
Daniel A. Connors , University of Colorado at Boulder
Tipp Moseley , University of Colorado at Boulder
Matthew Iyer , University of Colorado at Boulder
David Hodgdon , University of Colorado at Boulder
Dan Fay , University of Colorado at Boulder
pp. 34-43
III. Data Cache Optimization Techniques

Cooperative Caching with Keep-Me and Evict-Me (Abstract)

Subramaniam Venkiteswaran , University of Texas at Austin
Kathryn S. McKinley , University of Texas at Austin
Jennifer B. Sartor , University of Texas at Austin
Zhenlin Wang , Michigan Technological University
pp. 46-57

Hybrid Compiler and Microarchitecture Technique for Cache Traffic Optimization (Abstract)

Anasua Bhowmik , Indian Institute of Science, Bangalore, India
Mohamed Zahran , City College of New York of City University of New York, New York, NY
pp. 58-69

A Tile Size Selection Analysis for Blocked Array Layouts (Abstract)

Evangelia Athanasaki , National Technical University of Athens
Nectarios Koziris , National Technical University of Athens
Panayiotis Tsanakas , National Technical University of Athens
pp. 70-80
IV. Instrumentations and Compiler Optimizations

Automatic Low Overhead Program Instrumentation with the LOPI Framework (Abstract)

Lars Lundberg , Blekinge Institute of Technology, Sweden
Håkan Grahn , Blekinge Institute of Technology, Sweden
Simon Kågström , Blekinge Institute of Technology, Sweden
pp. 82-93

Optimizing Structures in Object Oriented Programs (Abstract)

Kaiyu Chen , Princeton University, Princeton, NJ
Sun Chan , Intel Labs, Intel Corporation, Santa Clara, CA
Roy Dz-Ching Ju , Intel Labs, Intel Corporation, Santa Clara, CA
Peng Tu , Intel Labs, Intel Corporation, Santa Clara, CA
pp. 94-103

Author Index (PDF)

pp. 105
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