The Community for Technology Leaders
2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004)
Madrid, Spain
Feb. 15, 2004 to Feb. 15, 2004
ISBN: 0-7695-2061-8
TABLE OF CONTENTS
Introduction

Program Committee (PDF)

pp. viii
Session I. Loop Optimization

Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling (Abstract)

Jan M? , Dresden University of Technology
Renate Merker , Dresden University of Technology
Dirk Fimmel , Dresden University of Technology
pp. 13-21
Session II. Garbage Collection
Session III. Energy Efficient Computing

Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction (Abstract)

C. Mani Krishna , University of Massachusetts at Amherst
Osman S. Unsal , Intel Labs UPC Barcelona
Israel Koren , University of Massachusetts at Amherst
Csaba Andras Moritz , University of Massachusetts at Amherst
pp. 43-52

Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded Systems (Abstract)

Fran?ois Bodin , IRISA, Campus Universitaire de Beaulieu
Gilles Pokam , IRISA, Campus Universitaire de Beaulieu
pp. 53-62
Session IV. Fast Simulation and I-Cache

SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing (Abstract)

Peter K. Szwed , Cornell University
Martin Schulz , Cornell University
Robert M. Buels , Cornell University
Sally A. McKee , Cornell University
Daniel Marques , Cornell University
pp. 65-74
Session V. Branch Optimizations

Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies (Abstract)

Manel Fernández , Universitat Politècnica de Catalunya
Roger Espasa , Universitat Politècnica de Catalunya
pp. 87-96

Reducing Fetch Architecture Complexity Using Procedure Inlining (Abstract)

Oliverio J. Santana , Universitat Politècnica de Catalunya
Alex Ramirez , Universitat Politècnica de Catalunya
Mateo Valero , Universitat Politècnica de Catalunya
pp. 97-106
Session VI. Data Cache Performance Optimization

Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache Locality (Abstract)

Evangelia Athanasaki , National Technical University of Athens
Nectarios Koziris , National Technical University of Athens
pp. 109-119

Data Movement Optimization for Software-Controlled On-Chip Memory (Abstract)

Hiroshi Nakamura , University of Tokyo
Masaaki Kondo , Japan Science and Technology Agency
Motonobu Fujita , University of Tokyo
pp. 120-127
Author Index

Author Index (PDF)

pp. 129
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