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Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures (2002)
Cambridge, Massachusetts
Feb. 3, 2002 to Feb. 3, 2002
ISBN: 0-7695-1534-7
Session I. Instruction Scheduling

Dynamically Scheduling VLIW Instructions with Dependency Information (Abstract)

Sunghyun Jee , University of Missouri at Columbia
Kannappan Palaniappan , University of Missouri at Columbia
pp. 15
Session II. Simulation and Profiling

On the Predictability of Program Behavior Using Different Input Data Sets (Abstract)

Wei Chung Hsu , University of Minnesota
Howard Chen , University of Minnesota
Pen Chung Yew , University of Minnesota
pp. 45
Session III. Data Access

A Study on Data Allocation of On-Chip Dual Memory Banks (Abstract)

Jeonghun Cho , Korea Advanced Institute of Science & Technology
Jinhwan Kim , Korea Advanced Institute of Science & Technology
Yunheung Paek , Korea Advanced Institute of Science & Technology
pp. 68
Session IV. Code Size

Code Size Efficiency in Global Scheduling for ILP Processors (Abstract)

Huiyang Zhou , North Carolina State University
Thomas M. Conte , North Carolina State University
pp. 79

Code Compression by Register Operand Dependency (Abstract)

Kelvin Lin , National Chiao Tung University
Jean Jyh-Jiun Shann , National Chiao Tung University
Chung-Ping Chung , National Chiao Tung University
pp. 91

Code Cache Management Schemes for Dynamic Optimizers (Abstract)

Kim Hazelwood , Harvard University
Michael D. Smith , Harvard University
pp. 102

Author Index (PDF)

pp. 111
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