Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance
Computer and Computational Sciences, International Multi-Symposiums on (2006)
Hangzhou, Zhejiang, China
June 20, 2006 to June 24, 2006
Jiangjiang Liu , Lamar University, USA
Brian Bell , Lamar University, USA
Tan Truong , Lamar University, USA
In order to achieve high instruction level parallelism (ILP), designers are turning to very long instruction word (VLIW) based designs, in which different types of instructions are grouped together as bundles of 128 bits or longer. In VLIW, the added nops increase the code size, limit processor performance by the under-utilization of functional units. In examining these performance issues of VLIW systems, we consider Intel first 64-bit architecture, the IA-64, and its first implementation, the Itanium, which employs Intel version of VLIW. We present a comprehensive analysis of the problem of under-utilization due to nops and stops across a wide range of application domains through the use of three different benchmark suites: SPEC CPU 2000, MediaBench, and PacketBench. Our results show that, on average, nops create an under-utilization factor of 28.46% in the case of SPEC CPU, 32.27% in MediaBench, and 29.76% in PacketBench. We also analyze the characteristics of different instruction bundle formats, which we obtain by collecting statistics concerning the frequency of the bundle formats.
T. Truong, B. Bell and J. Liu, "Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance," Computer and Computational Sciences, International Multi-Symposiums on(IMSCCS), Hangzhou, Zhejiang, China, 2006, pp. 389-396.