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2016 IEEE International Symposium on Workload Characterization (IISWC) (2016)
Providence, RI, USA
Sept. 25, 2016 to Sept. 27, 2016
ISBN: 978-1-5090-3897-8
pp: 1-10
Harshad Kasture , Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology
Daniel Sanchez , Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology
ABSTRACT
Latency-critical applications, common in datacenters, must achieve small and predictable tail (e.g., 95th or 99th percentile) latencies. Their strict performance requirements limit utilization and efficiency in current datacenters. These problems have sparked research in hardware and software techniques that target tail latency. However, research in this area is hampered by the lack of a comprehensive suite of latency-critical benchmarks. We present TailBench, a benchmark suite and evaluation methodology that makes latency-critical workloads as easy to run and characterize as conventional, throughput-oriented ones. TailBench includes eight applications that span a wide range of latency requirements and domains, and a harness that implements a robust and statistically sound load-testing methodology. The modular design of the TailBench harness facilitates multiple load-testing scenarios, ranging from multi-node configurations that capture network overheads, to simplified single-node configurations that allow measuring tail latency in simulation. Validation results show that the simplified configurations are accurate for most applications. This flexibility enables rapid prototyping of hardware and software techniques for latency-critical workloads.
INDEX TERMS
Benchmark testing, C++ languages, Hardware, Software, Microarchitecture, Robustness, Speech recognition,
CITATION
Harshad Kasture, Daniel Sanchez, "Tailbench: a benchmark suite and evaluation methodology for latency-critical applications", 2016 IEEE International Symposium on Workload Characterization (IISWC), vol. 00, no. , pp. 1-10, 2016, doi:10.1109/IISWC.2016.7581261
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