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Intelligent Information Hiding and Multimedia Signal Processing, International Conference on (2008)
Aug. 15, 2008 to Aug. 17, 2008
ISBN: 978-0-7695-3278-3
pp: 647-650
ABSTRACT
In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.
INDEX TERMS
lifting, discrete wavelet transform
CITATION

T. Shan, C. Lai, C. Hsieh and T. Tsai, "A Novel Efficient VLSI Architecture of 2-D Discrete Wavelet Transform," 2008 Fourth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), Harbin, 2008, pp. 647-650.
doi:10.1109/IIH-MSP.2008.275
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