The Community for Technology Leaders
2016 Seventh International Green and Sustainable Computing Conference (IGSC) (2016)
Hangzhou, China
Nov. 7, 2016 to Nov. 9, 2016
ISBN: 978-1-5090-5118-2
pp: 1-8
Mingzhe Zhang , Beijing Key Laboratory of Mobile Computing and Pervasive Device, ICT, CAS, China
Yangguang Shi , Beijing Key Laboratory of Mobile Computing and Pervasive Device, ICT, CAS, China
Fa Zhang , Key Lab of Intelligent Information Processing, ICT, CAS, Beijing, China
Zhiyong Liu , Beijing Key Laboratory of Mobile Computing and Pervasive Device, ICT, CAS, China
ABSTRACT
As the communication sub-system that connecting various on-chip components, Network-on-Chip (NoC) has a great influence on the performance of multi-/many-core processors. Because of NoC model contains a large number of parameters, the design space exploration (DSE) for NoC is a critical problem for the architects. Similar to the core design, existing DSE process mainly depends on iteratively time-consuming simulations. To lower the time budget, many previous studies focus on reducing the simulations. However, most of the proposed works based on regression or machine learning techniques, whose accuracy will be significantly affected by the scale of training set. It still needs a lot of simulations to build the training set.
INDEX TERMS
Routing, Reliability engineering, Training, Benchmark testing, Topology, Ports (Computers)
CITATION

Mingzhe Zhang, Yangguang Shi, Fa Zhang and Zhiyong Liu, "COMRANCE: A rapid method for Network-on-Chip design space exploration," 2016 Seventh International Green and Sustainable Computing Conference (IGSC), Hangzhou, China, 2016, pp. 1-8.
doi:10.1109/IGCC.2016.7892589
99 ms
(Ver 3.3 (11022016))