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IDDQ Testing, IEEE International Workshop on (1998)
San Jose, California
Nov. 12, 1998 to Nov. 13, 1998
ISBN: 0-8186-9191-3
Session 1: Keynote Address
Session 2: Effective IDDQ Testing

Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits (Abstract)

Toshimasa Kuchii , The University of Tokushima
Masaki Hashizume , The University of Tokushima
Takeomi Tamesada , The University of Tokushima
pp. 14
Session 3: New Approaches for Current-Based Testing
Session 4: Separating Good Chips from the Bad

Model-Based IDDQ Pass/Fail Limit Setting (Abstract)

T. Aruna Unni , Xilinx Corp.
D.M.H. Walker , Texas A&M University
pp. 43
Session 5: Core-Based Systems and Testability

100MHz IDDQ Sensor Design with 1(A Resolution for BIST Applications (Abstract)

Yann Antonioli , SHARP Corporation
Shigeki Nishikawa , SHARP Corporation
Hiroshi Uemura , SHARP Corporation
Kozo Kinoshita , Osaka University
pp. 64
Position Papers

Author Index (PDF)

pp. 82
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