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IDDQ Testing, IEEE International Workshop on (1997)
Washington, DC
Nov. 5, 1997 to Nov. 6, 1997
ISBN: 0-8186-8123-3
TABLE OF CONTENTS
Keynote Speech
Session 1: Test Generation and Testability: Chair: Adit Singh, Auburn University, USA

Iddq Test Pattern Generation for Scan Chain Latches and Flip-Flop (Abstract)

Samy R. Makar , Center for Reliable Computing Stanford University
Edward J. McCluskey , Center for Reliable Computing Stanford University
pp. 2

Random Testing with Partial Circuit Duplication and Monitoring IDDQ (Abstract)

Hiroshi Yokoyama , Akita University
Xiaoqing Wen , Akita University
Hideo Tamamoto , Akita University
pp. 7

IDDQ Testable Dynamic PLAs (Abstract)

Manoj Sachdev , Philips Research Laboratories
pp. 17
Session 2: Testing of Analog and Mixed Signal Circuits: Chair: Kozo Kinoshita, Osaka University, Japan

Current-Mode Techniques for Self-Testing Analogue Circuits (Abstract)

Iluminada Baturone , Instituto de Microelectronica de Sevilla (IMSE-CNM)
Santiago Sanchez-Solano , Instituto de Microelectronica de Sevilla (IMSE-CNM)
Jose L. Huertas , Instituto de Microelectronica de Sevilla (IMSE-CNM)
Andrew M. Richardson , Lancaster University
pp. 33
Session 3: Testing of Submicron ICs: Chair: Peter Maxwell, Hewlett Packard, USA

I/sub DDQ/ Testing Of A 180 Mhz Hp Pa-Risc Microprocessor With Redundancy Programmed Caches (Abstract)

T. Meneghini , Hewlett-Packard Co., Fort Collins, CO, USA
D. Josephson , Hewlett-Packard Co., Fort Collins, CO, USA
pp. 44
Session 4: Test Strategies: Chair: Monoj Sachdev, Philips Research Labs, The Netherlands

STBM: A Framework For Simulating And Selecting I/sub ddq/ Measurement Points For Leakage Faults (Abstract)

S. Chakravarty , State Univ. of New York, Buffalo, NY, USA
S.T. Zachariah , State Univ. of New York, Buffalo, NY, USA
P.J. Thadikaran , State Univ. of New York, Buffalo, NY, USA
pp. 58

A Hybrid (logic+I/sub DDQ/) Testing Strategy Using An Iterative Bridging Fault Filtering Scheme (Abstract)

Tzuhao Chen , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 63

Estimation Of Partition Size For I/Sub Ddq/ Testing Using Built-In Current Sensing (Abstract)

S.M. Menon , Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
M. Palmgren , Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
pp. 68

An Approach For Detecting Bridging Fault-Induced Delay Faults In Static CMOS Circuits Using Dynamic Power Supply Current Monitoring (Abstract)

A. Walker , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 73
Session 5: Limit Setting and Current Sensors: Chair: Yashwant K. Malaiya, Colorado State University, USA

A Simulation-Based Method for Estimating Defect-Free IDDQ (Abstract)

P.C. Maxwell , Hewlett-Packard Company
J.R. Rearick , Hewlett-Packard Company
pp. 80

On-Line CMOS BICS: An Experimental Study (Abstract)

Y. Maidon , UniversitT Bordeaux
Y. Deval , UniversitT Bordeaux
J. Tomas , UniversitT Bordeaux
F. Verdier , UniversitT Bordeaux
J.B. Begueret , UniversitT Bordeaux
J.P. Dom , UniversitT Bordeaux
pp. 85

A High-Speed Low-Voltage Built-In Current Sensor (Abstract)

Tsung-Chu Huang , Nat'l Cheng-Kung University, Taiwan
Min-Cheng Huang , Nat'l Cheng-Kung University, Taiwan
Kuen-Jong Lee , Nat'l Cheng-Kung University, Taiwan
pp. 90
Tutorial: Physical Failure Mechanisms, Reliability and IDDQ: Panel Chair: Chuck Hawkins, University of New Mexico, USA

Reliabilty, Test, and IDDQ Measurements (Abstract)

Charles F. Hawkins , University of New Mexico
Ali Keshavarzi , Intel Corp.
Jerry M. Soden , Sandia National Lab
pp. 96
Panel Session
Position Papers

Detecting Bridging Faults in Dynamic CMOS Circuits (Abstract)

Jonathan T.-Y. Chang , Center for Reliable Computing
Edward J. McCluskey , Center for Reliable Computing
pp. 106

A Current Sensing Circuit for Feedback Bridging Faults (Abstract)

Masaki Hashizume , The Univ. of Tokushima
Masahiro Ichimiya , The Univ. of Tokushima
Takeomi Tamesada , The Univ. of Tokushima
pp. 110

Simulation of Logic/IDDQ Tests for Resistive Shorts in Logic Circuits by Using Simplicial Approximation (Abstract)

Hung-Jen Lin , University of Maryland, College Park
Linda Milor , University of Maryland, College Park
pp. 114

Author Index (PDF)

pp. 119
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