2008 20th IEEE International Conference on Tools with Artificial Intelligence (2008)
Nov. 3, 2008 to Nov. 5, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICTAI.2008.55
Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.
FPGA, self-organizing feature map, placement, routing, constraints
W. L. Miranker, S. Xu and M. Maniatakos, "Constraint-Based Placement and Routing for FPGAs Using Self-Organizing Maps," 2008 20th IEEE International Conference on Tools with Artificial Intelligence(ICTAI), vol. 02, no. , pp. 465-469, 2008.