Systems and Networks Communication, International Conference on (2008)
Oct. 26, 2008 to Oct. 31, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICSNC.2008.13
This article describes the design and implementation of a channel equalizer for a terrestrial digital television (Digital Video Broadcasting-Terrestrial, DVB-T) on-channel repeater, namely gap-filler. Two are the benefits of including this equalizer in a repeater setup: on one hand, the transmitted signal requires a lower dynamic range and its degradation becomes smaller at the output amplifiers, thus allowing for a higher transmit power for the same modulation error rate (MER). On the other hand, it eases the equalization and decoding processes at the final receiver by improving its operation conditions. In this context, we present a novel low-cost equalizer architecture for mid-range and domestic gap-fillers. The design, implementation and validation methodology is also described, from the initial Matlab and Advanced Design System (ADS) simulations to the final hardware implementation, based on a field programmable gate array (FPGA) device and a Blackfin digital signal processor (DSP). The obtained practical results assess the performance gains predicted by simulation, hence proving the validity and efficacy of the designed equalizer to reduce the cost of the amplifiers and to obtain a better signal quality at the final user’s receiver.
DVB-T, Gap-filler, On-channel repeater, equalizer
R. Isasi, P. Prieto, J. D. Ser, I. Sobr? and M. Mendicute, "Design, Simulation and Implementation of a Channel Equalizer for DVB-T On-channel Repeaters," 2008 3rd International Conference on Systems and Networks Communications(ICSNC), Sliema, 2008, pp. 11-16.