2010 39th International Conference on Parallel Processing Workshops (2010)
San Diego, CA, USA
Sept. 13, 2010 to Sept. 16, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPPW.2010.37
Understanding and tuning the performance of complex applications on modern hardware are challenging tasks, requiring understanding of the algorithms, implementation, compiler optimizations, and underlying architecture. Many tools exist for measuring and analyzing the runtime performance of applications. Obtaining sufficiently detailed performance data and comparing it with the peak performance of an architecture are one path to understanding the behavior of a particular algorithm implementation. A complementary approach relies on the analysis of the source code itself, coupling it with a simplified architecture description to arrive at performance estimates that can provide a more meaningful upper bound than the peak hardware performance. We present a tool for estimating upper performance bounds of C/C++ applications through static compiler analysis. It generates parameterized expressions for different types of memory accesses and integer and floating-point computations. We then incorporate architectural parameters to estimate upper bounds on the performance of an application on a particular system. We present validation results for several codes on two architectures.
Static Compiler Analysis, Performance Bounds
B. Norris, S. H. Narayanan and P. D. Hovland, "Generating Performance Bounds from Source Code," 2010 39th International Conference on Parallel Processing Workshops(ICPPW), San Diego, CA, USA, 2010, pp. 197-206.