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2009 International Conference on Parallel Processing Workshops (2009)
Vienna, Austria
Sept. 22, 2009 to Sept. 25, 2009
ISSN: 1530-2016
ISBN: 978-0-7695-3803-7
pp: 520-527
ABSTRACT
This paper presents software support that enables seamless task restructuring and load balancing of pipelined applications at runtime, making it possible to dynamically pick the stages that will be executed as separate tasks on distinct CPUs, depending on the currently available resources and the execution context. This functionality is integrated in a development and execution framework for pipelined applications targeted at reconfigurable (in terms of interconnections), heterogeneous (in terms of architecture and/or clock speed), distributed memory, embedded Parallel Processor Arrays (PPAs). The primary motivation for this work is to support the use of PPA on-chip architectures, which are currently considered as dedicated accelerators, in a multitasking execution context where the available processor cores are distributed among concurrently executing applications. As a proof-of-concept, we discuss the execution of two pipelined applications on an FPGA-based prototype platform that features Xilinx Microblaze soft processor arrays.
INDEX TERMS
manycore, multitasking, dynamic load balancing
CITATION

D. Syrivelis and S. Lalis, "Supporting Multitasking of Pipelined Computations on Embedded Parallel Processor Arrays," 2009 International Conference on Parallel Processing Workshops(ICPPW), Vienna, Austria, 2009, pp. 520-527.
doi:10.1109/ICPPW.2009.25
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